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DATA SHEET
SAA7824 CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control (PhonIC)
Product specificationSupersedes data of 2003 Aug 07 2003 Oct 01
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control (PhonIC)
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.3 7.4 7.5 7.5.1 7.5.2 7.6 7.6.1 7.6.2 7.7 7.7.1 7.7.2 7.7.3 7.7.4 7.8 7.8.1 7.9 7.9.1 7.9.2 7.9.3 7.9.4 7.9.5 7.10 7.10.1 7.10.2 7.11 7.11.1 7.12 7.12.1 7.12.2 7.13 7.14 7.15 7.15.1 7.15.2 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Data acquisition and HF data path Decoder part Principle operating modes of the decoder Decoder speed and crystal frequency Lock-to-disc mode Standby modes Crystal oscillator Data slicer and bit clock regenerator DC offset cancellation Offset cancellation Reading back the DC offset value Demodulator Frame sync protection EFM demodulation Subcode data processing Q-channel processing EIAJ 3 and 4-wire subcode (CD graphics) interface V4 subcode interface CD text interface FIFO and error correction Flags output (CFLG) Audio functions De-emphasis and phase linearity Digital oversampling filter Concealment Mute, full-scale, attenuation and fade Peak detector Audio DAC interface Internal dynamic element matching digital-to-analog converter External DAC interface EBU interface Format KILL features The KILL circuit Silence injection Audio features off The versatile pins interface Spindle motor control Motor output modes Spindle motor operating modes 2 7.15.3 7.15.4 7.16 7.16.1 7.16.2 7.16.3 7.16.4 7.16.5 7.16.6 7.16.7 7.16.8 7.16.9 7.16.10 7.16.11 7.17 7.17.1 7.17.2 7.17.3 7.17.4 7.17.5 7.17.6 7.17.7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 16.5 17 18 19 20
SAA7824
Loop characteristics FIFO overflow Servo part Diode signal processing Signal conditioning Focus servo system Radial servo system Off-track counting Track counting modes Defect detection Off-track detection High-level features Driver interface Laser interface Microcontroller interface Microcontroller interface (4-wire bus mode) Microcontroller interface (I2C-bus mode) Decoder and shadow registers Summary of functions controlled by decoder registers 0 to F Summary of functions controlled by shadow registers Summary of servo commands Summary of servo command parameters SUMMARY OF SERVO COMMAND PARAMETERS VALUES LIMITING VALUES CHARACTERISTICS OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING) OPERATING CHARACTERISTICS (I2S-BUS TIMING) OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING) APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
2003 Oct 01
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
1 FEATURES
SAA7824
* Decoder and servo parts are based upon the SAA732X design (the original features are maintained) * Software compatibility is maintained with the SAA732X by using a similar register structure (new features are controlled from new shadow registers) * 1x, 2x and 4x speed * LF (servo) signals converted to digital representations by 6 oversampling bitstream ADCs * HF part summed from signals D1 to D4 and converted into a digital signal by a data slicer * On-chip buffering and filtering of the diode signals from the mechanism for signal optimization * Selectable DC offset cancellation of quiescent mechanism voltages and dark currents * On-chip laser power control (up to 120 mA) * Laser on/off control, including `soft' start control (zero to nominal power in 1 ms) * Monitor control and feedback circuit to maintain nominal output power throughout laser life * Dynamic element matching DAC with minimum external components * DAC performance of -80 dB Total Harmonic Distortion + Noise (THD + N) and 90 dB Signal-to-Noise Ratio (S/N) A-weighted * Separate left and right channel digital silence detection available on the KILL pins * Digital silence detection on internal data and loopback (external) data * 5 versatile pins, 2 inputs and 3 outputs * Integrated CD text decoder with separate microcontroller interface * Dedicated 4 MHz or 12 MHz clock output for microcontroller (configurable) * Configured for N-sub monitor diode * On-chip clock multiplier allows the use of an 8.4672 MHz crystal or ceramic resonator * The M1 version has an EBU mute function which allows independent muting of data being transmitted over the EBU interface whilst maintaining the SPDIF frame structure. 2 GENERAL DESCRIPTION
This document covers versions M0 and M1 of the CD audio decoder IC. The SAA7824 is a CD audio decoder IC which combines the function of the SAA732X IC with the pre-amplifier and laser control functions previously found in the TZA102X IC. The design is intended to reduce the external component count and hence the Bill Of Material (BOM). Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Compact Disc application.
2003 Oct 01
3
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
3 ORDERING INFORMATION TYPE NUMBER SAA7824HL PACKAGE NAME LQFP80 DESCRIPTION plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SAA7824
VERSION SOT315-1
4
QUICK REFERENCE DATA SYMBOL PARAMETER digital supply voltage analog supply voltage total supply current n = 1 mode n = 2 mode n = 4 mode CONDITIONS MIN. 1.65 3.0 - - - - 0 -55 - TYP. 1.8 3.3 38 39 40 8.4672 - - 90 MAX. 1.95 3.6 - - - - 70 +125 - V V mA mA mA MHz C C dB UNIT
VDDD VDDA IDD(tot)
fxtal Tamb Tstg S/NDAC
crystal frequency ambient temperature storage temperature onboard DAC signal-to-noise ratio
2003 Oct 01
4
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
5 BLOCK DIAGRAM
VSSA2 VSSA1 VSSA3 SENSE MONITOR R2 14 5 17 20 3 4
SAA7824
handbook, full pagewidth
D1 9 7 16
D2 10
D3 11
D4 12
R1 13
EXFILTER 2 LASER POWER CONTROL LOGIC
LPOWER 1 LASER 80 LASER
DC OFFSET COMPENSATION
VDDA1 VDDA2
MONITOR ADC
VOLTAGE BUFFER HF AND LF CAPTURE 6 8 BIAS GENERATOR CONTROL PART D1 TO D4 SUM
ANTI ALIAS 64 DISC ADC OUTPUT STAGES 65 66 HIGH-PASS FILTER CONTROL FUNCTION 15 CSLICE MOTO1 MOTO2
IREF VREFO
RA FO SL
SCL SDA RAB SILD TEST1 TEST2 TEST3 TEST4 OSCIN OSCOUT CLK16 CLK4/12 CDTRDY CDTDATA CDTCLK SFSY SUB RCK SBSY
53 52 54 55 76 77 78 79 19 18 49 50 36 37 38 59 58 57 60
MICROCONTROLLER INTERFACE
DATA SLICER AND THRESHOLD CONTROL
67 MOTOR CONTROL 68
TEST
DIGITAL PLL
ERROR CORRECTOR FLAGS 39 CFLAG
EFM DEMODULATOR TIMING SRAM CD TEXT INTERFACE AUDIO PROCESSOR EBU INTERFACE 62 45 48 47 46 44 43 42 27 22 23 26 25 24 21 29 32 30 31 DOBM EF SCLK WCLK DATA SCLI WCLI SDI DACVpos DACRP DACRN DACLP DACLN DACVref DACGND BUFINR BUFINL BUFOUTR BUFOUTL
MBL436
RAM ADDRESSER
SERIAL DATA INTERFACE SERIAL DATA (LOOPBACK) INTERFACE
INTERFACE CONTROL SUBCODE PROCESSOR
PEAK DETECT
SAA7824
DEM DAC
STATUS
56
DECODER MICROCONTROLLER INTERFACE
VERSATILE PINS INTERFACE
KILL HEADPHONE BUFFERS 34 LKILL 35 RKILL 33 28
RESET
51
40 VSSD1
61
69
41
63
70
71 72 73 74 75 V1 V2 V3 V4 V5
VSSD3 VDDD2 VSSD2 VDDD1 VDDD3
BUFVpos BUFGND
Fig.1 Block diagram.
2003 Oct 01
5
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
6 PINNING SYMBOL LFPOWER EXFILTER MONITOR SENSE VSSA1 IREF VDDA1 VREFO D1 D2 D3 D4 R1 R2 CSLICE VDDA2 VSSA2 OSCOUT OSCIN VSSA3 DACGND DACRP DACRN DACVref DACLN DACLP DACVpos BUFVpos BUFINR BUFOUTR BUFOUTL BUFINL BUFGND LKILL RKILL CDTRDY CDTDATA CDTCLK CFLAG VSSD1 2003 Oct 01 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I O I I SUP O SUP I/O I I I I I I I/O SUP SUP O I SUP I O O I/O O O I I I O O I I O O O O I O SUP laser power supply 10 nF capacitor for laser start-up control laser monitor diode OPU ground reference point for MONITOR measurement analog ground 1 DESCRIPTION
SAA7824
reference current output (24 k resistor connected to analog ground) analog supply voltage 1 servo reference voltage diode voltage/current input (central diode signal input) diode voltage/current input (central diode signal input) diode voltage/current input (central diode signal input) diode voltage/current input (central diode signal input) diode voltage/current input (satellite diode signal input) diode voltage/current input (satellite diode signal input) 10 nF capacitor for adaptive HF data slicer analog supply voltage 2 analog ground 2 crystal/resonator output crystal/resonator input analog ground 3 audio DAC ground audio DAC right channel differential positive output audio DAC right channel differential negative output audio DAC decoupling point (10 F or 100 nF to ground audio DAC left channel differential negative output audio DAC left channel differential positive output audio DAC positive supply voltage audio buffer positive supply voltage audio buffer right input audio buffer right output audio buffer left output audio buffer left input audio buffer ground KILL output for left channel (configurable as open-drain) KILL output for right channel (configurable as open-drain) CD text output to microcontroller ready flag CD text output data to microcontroller CD text microcontroller clock input correction flag output (open-drain) digital ground 1 6
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SYMBOL VDDD1 SDI WCLI SCLI EF DATA WCLK SCLK CLK16 CLK4/12 RESET SDA SCL RAB SILD STATUS RCK SUB SFSY SBSY VSSD2 DOBM VDDD2 RA FO SL MOTO1 MOTO2 VSSD3 VDDD3 V1 V2 V3 V4 V5 TEST1 TEST2 TEST3 TEST4 LASER 2003 Oct 01 PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I/O SUP I I I O O O O O O I I/O I I I O I O O O SUP O SUP O O O O O SUP SUP I I O O O I I I I O digital supply voltage 1 serial data input (loopback) word clock input (loopback) serial bit clock input (loopback) C2 error flag output serial data output word clock output serial clock output 16 MHz clock output configurable 4 MHz or 12 MHz clock output power-on reset input (active LOW) microcontroller interface data input/output (open-drain) microcontroller interface clock input DESCRIPTION
SAA7824
microcontroller interface R/W and load control input (4-wire) microcontroller interface R/W and load control input (4-wire) servo interrupt request line/decoder status register/DC offset value readback output subcode clock input P to W subcode output subcode frame sync output subcode block sync output digital ground 2 bi-phase mark output (externally buffered) digital supply voltage 2 radial actuator output focus actuator output sledge actuator output motor output 1 output motor output 2 output digital ground 3 digital supply voltage 3 versatile pin 1 input versatile pin 2 input versatile pin 3 output versatile pin 4 output versatile pin 5 output test pin 1 input test pin 2 input test pin 3 input test pin 4 input laser drive output 7
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SAA7824
68 MOTO2
67 MOTO1
70 VDDD3
63 VDDD2
69 VSSD3
handbook, full pagewidth
61 VSSD2 60 SBSY 59 SFSY 58 SUB 57 RCK 56 STATUS 55 SILD 54 RAB 53 SCL 52 SDA 51 RESET 50 CLK4/12 49 CLK16 48 SCLK 47 WCLK 46 DATA 45 EF 44 SCLI 43 WCLI 42 SDI 41 VDDD1 VSSD1 40
MBL437
80 LASER
79 TEST4
78 TEST3
77 TEST2
76 TEST1
LFPOWER EXFILTER MONITOR SENSE VSSA1 IREF VDDA1 VREFO D1
1 2 3 4 5 6 7 8 9
D2 10
SAA7824HL
D3 11 D4 12 R1 13 R2 14 CSLICE 15 VDDA2 16 VSSA2 17 OSCOUT 18 OSCIN 19 VSSA3 20 DACGND 21 DACRP 22 DACRN 23 DACVref 24 DACLN 25 DACLP 26 DACVpos 27 BUFVpos 28 BUFINR 29 BUFOUTR 30 BUFOUTL 31 BUFINL 32 BUFGND 33 LKILL 34 RKILL 35 CDTRDY 36 CDTDATA 37 CDTCLK 38 CFLAG 39
Fig.2 Pin configuration.
2003 Oct 01
8
62 DOBM
64 RA
65 FO
75 V5
74 V4
73 V3
72 V2
71 V1
66 SL
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
7 7.1 FUNCTIONAL DESCRIPTION Data acquisition and HF data path
SAA7824
The SAA7824 removes the need for an external diode signal pre-amplifier. A simplified diagram of the HF data path is illustrated in Fig.3. The high-pass filter, equalizing filter HF gain and adaptive slicer are all register programmable, thus enabling the SAA7824 to be optimized for the intended application.
handbook, full pagewidth
hf_gain 5:0 d1_hf d2_hf d3_hf d4_hf Vref op-amp bypass comp
summing amplifier
adaptive slicer
67.7 MHz sliced data
op-amp op-amp Vana
THRESHOLD CONTROL
high-pass filter
equalising filter
MBL438
Fig.3 Simplified block diagram of the HF data path and adaptive slicer.
7.2 7.2.1
Decoder part PRINCIPLE OPERATING MODES OF THE DECODER
7.2.3
LOCK-TO-DISC MODE
The decoding part supports a full audio specification and can operate at single-speed (n = 1), double-speed (n = 2) and quad-speed (n = 4). The factor `n' is called the overspeed factor. A simplified data flow through the decoder part is illustrated in Fig.7 for the M0 version and Fig.8 for the M1 version. 7.2.2 DECODER SPEED AND CRYSTAL FREQUENCY
For electronic shock absorption applications, the SAA7824 can be put into lock-to-disc mode. This allows Constant Angular Velocity (CAV) disc playback with varying input data rates from the inside-to-outside of the disc. In the lock-to-disc mode, the FIFO is blocked and the decoder will adjust its output data rate to the disc speed. Hence, the frequency of the I2S-bus (WCLK and SCLK) clocks are dependent on the disc speed. In the lock-to-disc mode there is a limit on the maximum variation in disc speed that the SAA7824 will follow. Disc speeds must always be within 25% to 100% range of their nominal value. The lock-to-disc mode is enabled or disabled by decoder register E.
The SAA7824 is a 1x, 2x and 4x (three-speed) decoding device, with an internal Phase-Locked Loop (PLL) clock multiplier. Table 1 gives the playback speeds that are achievable in conjunction with crystal frequency, mechanism, and internal clock settings (selectable via decoder register B).
2003 Oct 01
9
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
7.2.4 STANDBY MODES Table 1 Playback speeds REGISTER E 0XXX 0XXX 1XXX
SAA7824
The SAA7824 may be placed in two standby modes, selected by decoder register B (it should be noted that the device core is still active): * Standby 1: CD STOP mode; most I/O functions are switched off * Standby 2: CD PAUSE mode; audio output features are switched off, but the motor loop, the motor output and the subcode interfaces remain active; this is also called a `Hot Pause'. In the standby modes the various pins will have the following values: * MOTO1 and MOTO2: put in to high-impedance, PWM mode (Standby 1 and RESET: operating in Standby 2); put in high-impedance, PDM mode (Standby 1 and RESET: operating in Standby 2) * Pins SCL and SDA: no interaction; normal operation continues * Pins SCLK, WCLK, DATA, EF and DOBM: 3-state in both standby modes; normal operation continues after reset * Pins OSCIN, OSCOUT, CLK16 and CLK4/12: no interaction; normal operation continues * Pins V1 to V5 and CFLAG: no interaction; normal operation continues.
REGISTER B 0XXX 1XXX 0XXX
fxtal = 8.4672 MHz n=1 n = 2; voltage mode only n = 4; voltage mode only
7.3
Crystal oscillator
The crystal oscillator is a conventional 2-pin design which can also operate with ceramic resonators. The external components used around the crystal are illustrated in Fig.4 together with component values (C1 and C2) for a given crystal type given in Table 2. Oscillator frequencies that is used with the SAA7824 is 8.4672 MHz.
handbook, halfpage SAA7824
OSCILLATOR
OSCIN
XTAL
OSCOUT
C1
C2
MBL439
Fig.4 Crystal configuration.
Table 2
External capacitor selection based upon the crystal type MAXIMUM SERIES CRYSTAL RESISTANCE (RS) 8 MHz 10 pF 20 pF 30 pF <300 <300 <300 EXTERNAL LOAD CAPACITORS C1 8 pF 27 pF 47 pF C2 8 pF 27 pF 47 pF
CRYSTAL LOAD CAPACITANCE (CL)
2003 Oct 01
10
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
7.4 Data slicer and bit clock regenerator 7.5 DC offset cancellation
SAA7824
The SAA7824 has an integrated adaptive data slicer which is clocked at 67 MHz. The slice level is controlled by internal current sources which are switched onto and integrated by the external capacitor connected to the CSLICE pin. The currents are switched under the control of a Digital Phase-Locked loop (DPLL). Regeneration of the bit clock is achieved with an internal fully digital PLL. No external components are required and the bit clock is not output. The PLL has two registers (8 and 9) for selecting bandwidth and equalization. The PLL loop response is illustrated in Fig.5. For certain applications an off-track input is necessary. This is internally connected from the servo part (its polarity can be changed by the foc_parm1 parameter), but may be input via pin V1 if selected by register C. If this flag is HIGH, the SAA7824 will assume that its servo part is following the wrong track, and will flag all incoming HF data as incorrect.
Unwanted DC offsets can exist within the photo-diode signals and are defined as the DC present in the system when the laser diode is switched off. They arise from various sources of imperfection within the system such as leakage in the photo diodes and offsets in the Optical Pick-Up (OPU) circuitry. The SAA7824 is capable of measuring these offsets and minimizing them. 7.5.1 OFFSET CANCELLATION
A number of registers are associated with the DC offset cancellation function; these registers are given in Table 3. The measurement time of the DC offset is regulated by new shadow register C (bank 2). A longer time will yield more accurate results but will result in greater measurement durations. New shadow register 3 (bank 3) is used to select which diode is to be measured. 7.5.2 READING BACK THE DC OFFSET VALUE
handbook, halfpage
The microcontroller needs to be able to read the DC offset measurements in order to calculate the correct cancellation value [for writing back to new shadow register 7 (bank 3)]. This is achieved by using the STATUS pin and setting decoder register 7 to XX10. Shadow register C (bank 3) can then be used to control the STATUS pin output; the register settings are given in Table 20.
3. PLL, LPF
PLL loop response
f 2. PLL bandwidth 1. PLL integrator
MGS178
Once the measurement time has been set and the diode selected, the STATUS pin should be set to read the DC offset ready flag [new shadow register C (bank 3) = X01X]. This signal will toggle HIGH after the prescribed measurement time. Changing the diode selection will result in the measurement timer being automatically reset. The microcontroller can read back the measurement by setting the STATUS pin to output the DC offset value [new shadow register C (bank 3) = X10X]. The offset value is repeatedly streamed out through the STATUS pin and is UART compatible. It should be noted that the MSB is inverted and will require re-inverting after the offset value has been captured. Timing information for this signal is illustrated in Fig.6. The final DC cancellation value (as calculated by the microcontroller) can then be written to new shadow register 7 (bank 3). This is a multiple write register containing the cancellation values for all six diodes.
Points 1, 2 and 3 are all programmable via decoder register 8.
Fig.5 Digital PLL loop response.
2003 Oct 01
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Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 3 Registers relating to the DC offset cancellation SHADOW REGISTER C DC offset measurement times 3 diode selection for DC offset measurement ADDRESS 1100 DATA XX00 XX01 XX10 XX11 11 (bank 3) 0011 0000 0001 0010 0011 0100 0101 0110 0111 C STATUS pin control 1100 X00X FUNCTION settling time = 354 s settling time = 1 ms settling time = 2 ms settling time = 10 ms select D1 select D1 select D2 select D3 select D4 select R1 select R2 select D1 STATUS pin outputs decoder status register information STATUS pin outputs DC offset ready flag STATUS pin outputs DC offset value DC cancellation values for diodes D1 to D4 and R1 and R2; see Table 20
SAA7824
SHADEN BITS 10 (bank 2)
INITIAL reset - - - reset - - - - - - - reset
X01X X10X 7 DC cancellation levels 0111 multi-write (9 x 4 bits)
- - -
handbook, full pagewidth
2.19/n s D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MBL440
272.1/n s
Fig.6 Serial data format for DC offset data.
2003 Oct 01
12
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output from data slicer
Philips Semiconductors
handbook, full pagewidth
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
new shadow register 7 bank 2: 0XXX = pass all data 1XXX = pass correct data only
CD TEXT INTERFACE
CDTRDY CDTCLK CDTDATA
1 0
V4
RCK
0: register D = XX01
CD GRAPHICS INTERFACE
SBSY SFSY SUB MICROCONTROLLER INTERFACE SDA
V4 SUBCODE INTERFACE register F SUBCODE PROCESSOR
EBU INTERFACE
DOBM
DIGITAL PLL AND DEMODULATOR
1: decoder register A = XX0X 0: decoder register A XX1X
decoder register A
1: shadow register 7 = XX1X 0: shadow register 7 = XX0X SCLK WCLK DATA EF DACRP DACLP DACRN DACLN
1 0 1: decoder register 3 = XX10 (1fs mode) 0: decoder register 3 XX10 1: no pre-emphasis detected OR register D = 01XX (de-emphasis signal at V5) 0: pre-emphasis detected AND register D 01XX
1 0
13
FIFO ERROR CORRECTOR FADE/MUTE/ INTERPOLATE
ONBOARD DAC
1 DIGITAL FILTER 0
PHASE COMPENSATION
1 0 1 0 1 0 I2S/EIAJ BUS INTERFACE 1 0
decoder register 3 INTERNAL KILL
DE-EMPHASIS FILTER decoder register 3 0 LKILL RKILL
1: shadow register 7 = XX1X 0: shadow register 7 = XX0X I2S/EIAJ LOOPBACK INTERFACE
decoder register C
loopback KILL
1
Product specification
0: new shadow register A bank 2 = 0XXX 1: new shadow register A bank 2 = 1XXX
1: decoder register 3 101X 0: decoder register 3 = 101X (CD-ROM modes)
WCLI SCLI SDI
MGS180
SAA7824
Fig.7 Simplified data flow of decoder functions for the M0 version.
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output from data slicer
Philips Semiconductors
handbook, full pagewidth
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
new shadow register 7 bank 2: 0XXX = pass all data 1XXX = pass correct data only
CD TEXT INTERFACE
CDTRDY CDTCLK CDTDATA
1 0
V4
RCK
0: register D = XX01
CD GRAPHICS INTERFACE
SBSY SFSY SUB MICROCONTROLLER INTERFACE SDA
V4 SUBCODE INTERFACE register F SUBCODE PROCESSOR
Mute Bypass (Shadow Register 7 Bank 1) Activate Mute (Decoder Reg 0) DIGITAL PLL AND DEMODULATOR 1: decoder register A = XX0X 0: decoder register A = XX1X Hard Mute (Decoder Reg C) EBU MUTE
EBU INTERFACE
DOBM
decoder register A
1: shadow register 7 = XX1X 0: shadow register 7 = XX0X SCLK WCLK DATA EF DACRP DACLP DACRN DACLN
1 0 1: decoder register 3 = XX10 (1fs mode) 0: decoder register 3 XX10 1: no pre-emphasis detected OR register D = 01XX (de-emphasis signal at V5) 0: pre-emphasis detected AND register D 01XX
1 0
14
FIFO ERROR CORRECTOR FADE/MUTE/ INTERPOLATE
ONBOARD DAC
1 DIGITAL FILTER 0
PHASE COMPENSATION
1 0 1 0 1 0 I2S/EIAJ BUS INTERFACE 1 0
decoder register 3 INTERNAL KILL
DE-EMPHASIS FILTER decoder register 3 1 LKILL RKILL
1: shadow register 7 = XX1X 0: shadow register 7 = XX0X I2S/EIAJ LOOPBACK INTERFACE
decoder register C
loopback KILL
0
Product specification
0: new shadow register A bank 2 = 0XX 1: new shadow register A bank 2 = 1XXX
1: decoder register 3 101X 0: decoder register 3 = 101X (CD-ROM modes)
WCLI SCLI SDI
MDB501
SAA7824
Fig.8 Simplified data flow of decoder functions for the M1 version.
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
7.6 7.6.1 Demodulator FRAME SYNC PROTECTION 7.7.3 V4 SUBCODE INTERFACE
SAA7824
A double timing system is used to protect the demodulator from erroneous sync patterns in the serial data. The master counter is only reset if: * A sync coincidence is detected; sync pattern occurs 588 1 EFM clocks after the previous sync pattern * A new sync pattern is detected within 6 EFM clocks of its expected position. The sync coincidence signal is also used to generate the PLL lock signal, which is active HIGH after 1 sync coincidence is found, and reset LOW if during 61 consecutive frames no sync coincidence is found. The PLL lock signal can be accessed via the SDA or STATUS pins selected by decoder registers 2, 7 and new shadow register C (bank 3). Also incorporated in the demodulator is a Run Length 2 (RL2) correction circuit. Every symbol detected as RL2 will be pushed back to RL3. To do this, the phase error of both edges of the RL2 symbol are compared and the correction is executed at the side with the highest error probability. 7.6.2 EFM DEMODULATION
Data of subcode channels, Q-to-W, may be read via pin V4 if selected via decoder register D. The format is similar to RS232 and is illustrated in Fig.10. The subcode sync word is formed by a pause of (200/n) s minimum. Each subcode byte starts with a logic 1 followed by 7 bits (Q-to-W). The gap between bytes is variable between (11.3/n) s and (90/n) s. The subcode data is also available in the EBU output (DOBM) in a similar format. 7.7.4 CD TEXT INTERFACE
R-to-W subcode data is captured and stored until a complete CD text PACK is formed. The least significant 16 bits of the PACK are used for a CRC. The behaviour of the CD text interface is controlled by new shadow register 7 (bank 2). The interface can either flag all data (i.e. passed or failed CRC) or it can flag good data only. The data ready flag is monitored via pin CDTRDY and is active LOW. The pulse width varies from 73/n s, for the first three packs, to 317/n s for the fourth pack. When a PACK becomes available, the initial value of the CDTDATA pin indicates the CRC result (HIGH = passed; LOW = failed). The microcontroller can fetch the data by applying a clock signal (maximum frequency = 5 MHz) to pin CDTCLK and reading the subsequent bitstream on pin CDTDATA. The 128 data bits are streamed out LSB first. A complete CD text PACK consists of 4 header bytes, 12 data bytes, and 2 CRC bytes although the latter 2 bytes are dropped internally once the CRC calculation is complete. Please refer to the "Red Book" for further details relating to the format of a CD text PACK The timing diagram for the CD text interface is illustrated in Fig.11.
The 14-bit EFM data and subcode words are decoded into 8-bit symbols. 7.7 7.7.1 Subcode data processing Q-CHANNEL PROCESSING
The 96-bit Q-channel word is accumulated in an internal buffer. The last 16 bits are used internally to perform a Cyclic Redundancy Check (CRC). If the data is good, the SUBQREADY-I signal will go LOW. SUBQREADY-I can be read via the SDA or STATUS pins, selected via decoder registers 2, 7 and new shadow register C (bank 3). Good Q-channel data may be read from pin SDA. 7.7.2 EIAJ 3 AND 4-WIRE SUBCODE (CD GRAPHICS)
INTERFACE
Data from all the subcode channels (P-to-W) may be read via the subcode interface, which conforms to EIAJ CP-2401. The interface is enabled and configured as either a 3 or 4-wire interface via decoder register F. The subcode interface output formats are illustrated in Fig.9, where the RCK signal is supplied by another device such as a CD graphics decoder.
2003 Oct 01
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Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SAA7824
handbook, full pagewidth
SF0
SF1
SF2
SF3
SF97
SF0
SF1
SBSY SFSY RCK P-W SUB EIAJ 4-wire subcode interface P-W P-W
SF0 SFSY RCK
SF1
SF2
SF3
SF97
SF0
SF1
P-W SUB
P-W
P-W
EIAJ 3-wire subcode interface
SFSY RCK P SUB Q R S T U V W
MBG410
Fig.9 EIAJ subcode (CD graphics) interface format.
2003 Oct 01
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Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SAA7824
200/n s min W96 1
11.3/n s Q R S T U V W
11.3/n s min 90/n s max 1 Q
MBG401
Where n = disc speed.
Fig.10 Subcode format and timing on pin V4.
73/n s to 317/n s
handbook, full pagewidth
CDTRDY
CDTCLK CRC flag D0 D1 D2 D3 D126 D127
MBL441
CDTDATA
~1/n ns 200 ns (min)
Where n = disc speed.
Fig.11 CD text interface format and timing.
7.8
FIFO and error correction
7.8.1
FLAGS OUTPUT (CFLG)
The SAA7824 has a 8 frame FIFO. The error corrector is a t = 2, e = 4 type, with error corrections on both C1 (32 symbol) and C2 (28 symbol) frames. Four symbols are used from each frame as parity symbols. This error corrector can correct up to two errors on the C1 level and up to four errors on the C2 level. The error corrector also contains a flag processor. Flags are assigned to symbols when the error corrector cannot ascertain if the symbols are definitely good. C1 generates output flags which are read after de-interleaving by C2, to help in the generation of C2 output flags. The C2 output flags are used by the interpolator for concealment of uncorrectable errors. They are also output via the EBU signal (DOBM). The EF output will flag bytes in error in both audio and CD-ROM modes.
The flags output pin CFLG shows the status of the error corrector and interpolator and is updated every frame (7.35 x n kHz). In the SAA7824, 8 x 1-bit flags are present on the CFLG pin as illustrated in Fig.12. This signal shows the status of the error corrector and interpolator. The first flag bit, F1, is the absolute time sync signal, the FIFO-passed subcode sync and relates the position of the subcode sync to the audio data (DAC output). This flag may also be used in a super FIFO or in the synchronization of different players. The output flags can be made available at bit 4 of the EBU data format (LSB of the 24-bit data word), if selected by decoder register A.
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Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SAA7824
handbook, full pagewidth
33.9/n s F8
11.3/n s F1 F2 F3 F4 F5 F6 F7 F8
33.9/n s F1
MBG425
Where n = disc speed.
Fig.12 Flag output timing diagram.
Table 4 F1 0 1 X X X X X X X X X X X X X X
Output flags F2 X X 0 0 1 1 X X X X X X X X X X F3 X X 0 1 0 1 X X X X X X X X X X F4 X X X X X X 0 0 0 0 1 1 X X X X F5 X X X X X X 0 0 1 1 0 1 X X X X F6 X X X X X X X X X X X X 0 0 1 1 F7 X X X X X X X X X X X X 0 1 0 1 F8 X X X X X X 0 1 0 1 0 1 X X X X DESCRIPTION no absolute time sync absolute time sync C1 frame contained no errors C1 frame contained 1 error C1 frame contained 2 errors C1 frame uncorrectable C2 frame contained no errors C2 frame contained 1 error C2 frame contained 2 errors C2 frame contained 3 errors C2 frame contained 4 errors C2 frame uncorrectable no interpolations at least one 1-sample interpolation at least one hold and no interpolations at least one hold and one 1-sample interpolation
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Philips Semiconductors
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CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
7.9 7.9.1 Audio functions DE-EMPHASIS AND PHASE LINEARITY 7.9.3 CONCEALMENT
SAA7824
When pre-emphasis is detected in the Q-channel subcode, the digital filter automatically includes a de-emphasis filter section. When de-emphasis is not required, a phase compensation filter section controls the phase of the digital oversampling filter to 1 within the band 0 to 16 kHz. With de-emphasis the filter is not phase linear. If the de-emphasis signal is set to be available at pin V5, selected via decoder register D, then the de-emphasis filter is bypassed. 7.9.2 DIGITAL OVERSAMPLING FILTER
A 1-sample linear interpolator becomes active if a single sample is flagged as erroneous but cannot be corrected. The erroneous sample is replaced by a level midway between the preceding and following samples. Left and right channels have independent interpolators. If more than one consecutive non-correctable sample is found, the last good sample is held. A 1-sample linear interpolation is then performed before the next good sample; see Fig.13. In CD-ROM modes (i.e. the external DAC interface is selected to be in a CD-ROM format) concealment is not executed. 7.9.4 MUTE, FULL-SCALE, ATTENUATION AND FADE
For optimizing performance with an external DAC, the SAA7824 contains a 2 to 4 times oversampling IIR filter. The filter specification of the 4 times oversampling filter is given in Table 5. These attenuations do not include the sample-and-hold at the external DAC output or the DAC post filter. When using the oversampling filter, the output level is scaled -0.5 dB down to avoid overflow on full-scale sine wave inputs (0 to 20 kHz). Table 5 Filter specification STOP BAND - - 24 kHz 24 to 27 kHz 27 to 35 kHz 35 to 64 kHz 64 to 68 kHz 68 kHz 69 to 88 kHz ATTENUATION 0.001 dB 0.03 dB 25 dB 38 dB 40 dB 50 dB 31 dB 35 dB 40 dB
A digital level controller is present on the SAA7824 which performs the functions of soft mute, full-scale, attenuation and fade; these are selected via decoder register 0: * Mute: signal reduced to 0 in a maximum of 128 steps; 3/n ms * Attenuation: signal scaled by -12 dB * Full-scale: ramp signal back to 0 dB level; from mute it takes 3/n ms * Fade: activates a 128 stage counter which allows the signal to be scaled up or down in 0.07 dB steps - 128 = full-scale - 120 = -0.5 dB (i.e. full-scale if oversampling filter is used) - 32 = -12 dB - 0 = mute. 7.9.5 PEAK DETECTOR
PASS BAND 0 to 9 kHz 19 to 20 kHz - - - - - - -
The peak detector measures the highest audio level (absolute value) on positive peaks for left and right channels. The 8 most significant bits are output in the Q-channel data in place of the CRC bits. Bits 81 to 88 contain the left peak value (bit 88 = MSB) and bits 89 to 96 contain the right peak value (bit 96 = MSB). The values are reset after reading Q-channel data via pin SDA.
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Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SAA7824
Interpolation
Hold
Interpolation
OK
Error
OK
Error
Error
Error
OK
OK
MGA372
Fig.13 Concealment mechanism.
7.10 7.10.1
Audio DAC interface INTERNAL DYNAMIC ELEMENT MATCHING DIGITAL-TO-ANALOG CONVERTER
The onboard audio DEM DAC operates at an oversampling rate of 96fs and is designed for operation with an audio input at 1fs. The DAC is equipped with two pairs of stereo outputs for driving medium impedance line outputs and for directly driving low impedance headphones. A pair of analog inputs are provided to enable external audio sources to make use of the headphone output buffers. Audio data from the decoder part of the SAA7824 can be routed as described in Sections 7.10.1.1 and 7.10.1.2. Table 6 Shadow register SHADOW REGISTER 7 control of onboard DAC ADDRESS 0111 DATA 0000 FUNCTION use external DAC or route audio data back into onboard DAC (loopback mode) route audio data directly into onboard DAC (non-loopback mode) RESET reset
SHADEN BITS 01 (bank 1)
0010
-
7.10.1.1
Use of internal DAC
Setting shadow register 7 to 0010 will route audio data from the decoder into the internal DAC. To enable the on-board DAC, the DAC interface format (set by register 3) must be set to 16-bit 1fs mode, either I2S-bus or EIAJ format. CD-ROM mode can also be used if interpolation is not required. The serial data output pins for interfacing with an external DAC (SCLK, WCLK, DATA and EF) are set to high-impedance.
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CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
7.10.1.2 Loopback external data into onboard DAC
SAA7824
The onboard DAC can also be set to accept serial data inputs from an external source, e.g. an Electronic Shock Absorption (ESA) IC. This is known as loopback mode and is enabled by setting shadow register 7 to 0000. This enables the serial data output pins (SCLK, WCLK, DATA and EF) so that data can be routed from the SAA7824 to an external ESA system (or external DAC). The serial data from an external ESA IC can then also be input to the onboard DAC on the SAA7824 by utilising the serial data input interface (SCLI, SDI and WCLI). In this mode, a wide range of data formats to the external ESA IC can be programmed as shown in Table 7. However, the serial input on the SAA7824 will always expect the input data from the ESA IC to be 16-bit 1fs and the same data format, either I2S-bus or EIAJ, as the serial output format (set by decoder register 3). 7.10.2 EXTERNAL DAC INTERFACE
The SAA7824 is compatible with a wide range of external DACs. Eleven formats are supported and are given in Table 7. Figures 14 and 15 show the Philips I2S-bus and the EIAJ data formats respectively. When the decoder is operated in lock-to-disc mode, the SCLK frequency is dependent on the disc speed factor `d'. All formats are MSB first and 1fs is 44.1 kHz. The polarity of the WCLK and the data can be inverted; selectable by decoder register 7. It should be noted that EF is only a defined output in CD-ROM and 1fs modes. When using an external DAC (or when using the onboard DAC in non-loopback mode), the serial data inputs to the onboard DAC (SCLI, SDI and WCLI) should be tied to ground.
Audio data from the SAA7824 can be sent to an external DAC, identical to the SAA732x series, in `loopback' mode (i.e. shadow register 7 is set to 0000). Table 7 DAC interface formats SAMPLE FREQUENCY fs fs fs fs fs 4fs 4fs 4fs 2fs 2fs 2fs NUMBER OF BITS 16 16 16/18(1) 16 18 16 18 18 16 18 18 SCLK (MHz) 2.1168 x n 2.1168 x n 2.1168 x n 2.1168 x n 2.1168 x n 8.4672 x n 8.4672 x n 8.4672 x n 4.2336 x n 4.2336 x n 4.2336 x n FORMAT CD-ROM (I2S-bus) CD-ROM (EIAJ) Philips 16/18 bits(1) I2S-bus INTERPOLATION no no yes yes yes yes yes yes yes yes yes
REGISTER 3 1010 1011 1110 0010 0110 0000 0100 1100 0011 0111 1111 Note
EIAJ 16 bits EIAJ 18 bits EIAJ 16 bits EIAJ 18 bits Philips I2S-bus 18 bits EIAJ 16 bits EIAJ 18 bits Philips I2S-bus 18 bits
1. In this mode the first 16 bits contain data, but if any of the fade, attenuate or de-emphasis filter functions are activated then the first 18 bits contain data.
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SCLK DATA 1 0 15 14 1 LEFT CHANNEL DATA (WCLK NORMAL POLARITY) 0 15 14 WCLK EF LSB error flag (CD-ROM AND 1fs MODES ONLY) MSB error flag LSB error flag MSB error flag
MBG424
Philips Semiconductors
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Fig.14 Philips I2S-bus data format (16-bit word length). 22
SCLK DATA 0 17 LEFT CHANNEL DATA WCLK
EF (CD-ROM AND 1fs MODES ONLY)
0
17
MSB error flag
LSB error flag
MSB error flag
MBG423
Product specification
SAA7824
Fig.15 EIAJ data format (18-bit word length).
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
7.11 EBU interface
SAA7824
The bi-phase mark digital output signal at pin DOBM is in accordance with the format defined by the IEC 60958 specification. Three different modes can be selected via decoder register A: * DOBM pin held LOW * Data taken before concealment, mute and fade (must always be used for CD-ROM modes) * Data taken after concealment, mute and fade. An additional mute function is available via shadow register 7 (bank 1) and decoder register 0 and C. They provide the following: * Hard mute: immediate mute of the audio sample in the ROM mode at 1x, 2x or 4x Table 8 EBU frame format; see also Table 9 BITS 0 to 3 4 to 7 4 8 to 27 28 29 30 - not used; normally zero
* Soft mute: 3 ms ramp up or ramp down of the audio samples in the 1x audio mode * Bypass: switches the EBU mute function out of the EBU signal path. 7.11.1 FORMAT
The digital audio output consists of 32-bit words (`subframes') transmitted in bi-phase mark code (two transitions for a logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384. The EBU frame format is given in Table 8.
FUNCTION Sync Auxiliary Error flags Audio sample Validity flag User data Channel status Table 9
DESCRIPTION
CFLG error and interpolation flags when selected by register A first 4 bits not used (always zero); twos complement; LSB = bit 12, MSB = bit 27 valid = logic 0 used for subcode data (Q-to-W) control bits and category code
Description of EBU frame function DESCRIPTION The sync word is formed by violation of the bi-phase rule and therefore does not contain any data. Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations: sync B; start of a block (384 words), word contains left sample; sync M; word contains left sample (no block start) and sync W; word contains right sample. Left and right samples are transmitted alternately. Audio samples are flagged (bit 28 = 1) if an error has been detected but was uncorrectable. This flag remains the same even if data is taken after concealment. Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is asynchronous with the block rate. The channel status bit is the same for left and right words. Therefore a block of 384 words contains 192 channel status bits. The category code is always CD. The bit assignment is given in Table 10.
FUNCTION Sync
Audio sample Validity flag User data Channel status
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Table 10 Bit assignment FUNCTION Control Reserved mode Category code Clock accuracy Remaining BITS 0 to 3 4 to 7 8 to 15 28 to 29 6 to 27 and 30 to 191 DESCRIPTION
SAA7824
copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when copy permitted; bit 3 is logic 1 when recording has pre-emphasis always zero CD: bit 8 = logic 1, all other bits = logic 0 set by register A; 10 = level I; 00 = level II; 01 = level III always zero
7.12 7.12.1
KILL features THE KILL CIRCUIT
7.13
Audio features off
The KILL circuit detects digital silence by testing for an all-zero or all-ones data word in the left and right channels. This occurs in two places; prior to the digital filter (internal KILL), and in the digital DAC (loopback/external KILL). Programming bit 3 of new shadow register A (bank 2) determines whether internal or external data is used. The output is switched to active HIGH when silence has been detected for at least 270 ms, or if mute is active, or in CD-ROM mode. Two KILL modes are available which can be selected by decoder register C: * Mono KILL: LKILL and RKILL are both active HIGH when silence is detected on left and right channels simultaneously * Stereo KILL: LKILL and RKILL are active HIGH independently of each other when silence is detected on either channel. 7.12.2 SILENCE INJECTION
The audio features can be turned off (selected by decoder register E) and will affect the following functions: * Digital filter, fade, peak detector, internal KILL circuit (although RKILL and LKILL outputs still active) are disabled * V5 (if selected to be the de-emphasis flag output) and the EBU outputs become undefined. The EBU output should be set LOW prior to switching the audio features off and after switching the audio features back on, a full-scale command should be given. 7.14 The versatile pins interface
The SAA7824 has five pins that can be reconfigured for different applications. The functions of these versatile pins are identical to the SAA732x series and can be programmed by decoder registers C, D and shadow register 3 (bank 1) as shown in Table 11.
The silence inject function monitors the left and right KILL signals and forces the analog DAC into silence when KILL is asserted. This improves the internal Signal-to-Noise Ratio (SNR) by preventing any spurious noise from reaching the DAC. The silence inject function can be enabled or disabled by programming bit 2 of the new shadow register A (bank 2).
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CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 11 Pin applications PIN NAME V1 PIN NUMBER 71 TYPE input REGISTER REGISTER ADDRESS DATA 1100 - V2 V3 V4 72 73 74 input output output - 1100 - 1101 - - - V5 75 output 1101 - - 7.15 7.15.1 Spindle motor control MOTOR OUTPUT MODES XXX1 XXX0 - 00XX 01XX 0000 XX01 XX10 XX11 01XX 10XX 11XX FUNCTION external off-track signal input
SAA7824
internal off-track signal used input may be read via decoder status bit; selected via register 2 input may be read via decoder status bit; selected via register 2 output = 0 output = 1 4-line motor drive (using V4 and V5) Q-to-W subcode output output = 0 output = 1 de-emphasis output (active HIGH) output = 0 output = 1
7.15.1.1
Pulse density output mode
The spindle motor speed is controlled by a fully integrated digital servo. Address information from the internal 8 frame FIFO and disc speed information are used to calculate the motor control output signals. Several output modes, selected by decoder register 6, are supported: * Pulse density, 2-line (true complement output), (1 x n) MHz sample frequency * PWM output, 2-line, (22.05 x n) kHz modulation frequency * PWM output, 4-line, (22.05 x n) kHz modulation frequency * CDV motor mode.
In the pulse density mode the motor output pin (MOTO1) is the pulse density modulated motor output signal. A 50% duty factor corresponds with the motor not actuated, higher duty factors mean acceleration, lower duty factors means braking. In this mode, the MOTO2 signal is the inverse of the MOTO1 signal. Both signals change state only on the edges of a (1 x n) MHz internal clock signal.
7.15.1.2
PWM output mode (2-line)
In the PWM mode the motor acceleration signal is put in pulse-width modulation form on the MOTO1 output. The motor braking signal is pulse-width modulated on the MOTO2 output. The timing is illustrated in Fig 16. A typical application diagram is illustrated in Fig 17.
t rep = 45 s MOTO1 MOTO2
t dead
240 ns
Accelerate
Brake
MGA366
Fig.16 2-line PWM mode timing.
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Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SAA7824
+
M 10 100 nF
MOTO1
MOTO2
VSS
MGA365 - 2
Fig.17 Motor 2-line PWM mode application diagram.
7.15.1.3
PWM output mode (4-line)
Using two extra outputs from the versatile pins interface, it is possible to use the SAA7824 with a 4-input motor bridge. The timing is illustrated in Fig 18. A typical application diagram is illustrated in Fig 19.
t rep = 45 s MOTO1 MOTO2 V4 V5
t dead
240 ns
t ovl = 240 ns
MGA367 - 1
Accelerate
Brake
Fig.18 4-line PWM mode timing.
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Philips Semiconductors
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CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SAA7824
+
V4
V5
M 10 100 nF
MOTO1
MOTO2
VSS
MGA364 - 2
Fig.19 Motor 4-line PWM mode application diagram.
7.15.1.4
CDV/CAV output mode
7.15.2.1
Motor OV flag
In the CDV motor mode, the FIFO position will be put in pulse-width modulated form on the MOTO1 pin [carrier frequency (300 x d) Hz], where `d' is the disc speed factor. The PLL frequency signal will be put in pulse-density modulated form (carrier frequency 4.23 x n MHz) on the MOTO2 pin. The integrated motor servo is disabled in this mode. The PWM signal on MOTO1 corresponds to a total memory space of 20 frames, therefore the nominal FIFO position (half full) will result in a PWM output of 60%. In the lock-to-disc (CAV) mode the CDV motor mode is the only mode that can be used to control the motor. 7.15.2 SPINDLE MOTOR OPERATING MODES
The SAA7824 contains a servo loop that is used to regulate the spindle speed. The motor OV flag is provided to indicate when the motor output has overloaded. During a large change in disc speed i.e. by a long jump or x-factor change, the motor OV flag will be asserted due to the full and longer duration required to attain the new desired speed. The OV flag indicates when the internal processes of the modulator have overflowed and not necessarily when the output power has reached 100%. Similarly, the flag does not fall at a specific output power level but at a specific speed error level. The error level at which the flag falls is determined by the selected servo gain, and will be internally equivalent to +3 x gain or -3 x gain.
The operating modes of the motor servo are controlled by decoder register 1; see Table 12. In the SAA7824 decoder there is an anti-windup mode for the motor servo, selected via decoder register 1. When the anti-windup mode is activated the motor servo integrator will hold if the motor output saturates.
7.15.2.2
Power limit
In start mode 1, start mode 2, stop mode 1 and stop mode 2, a fixed positive or negative voltage is applied to the motor. This voltage can be programmed as a percentage of the maximum possible voltage, via register 6, to limit current drain during start and stop. The following power limits are possible: * 100% (no power limit), 75%, 50% or 37% of maximum.
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CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
7.15.3 LOOP CHARACTERISTICS
SAA7824
The gain and crossover frequencies of the motor control loop can be programmed via decoder registers 4 and 5. The following parameter values are possible: * Gains: 3.2, 4.0, 6.4, 8.0, 12.8, 16, 25.6 and 32 * Crossover frequency f4: 0.5 x n Hz, 0.7 x n Hz, 1.4 x n Hz and 2.8 x n Hz * Crossover frequency f3: 0.85 x n Hz, 1.71 x n Hz and 3.42 x n Hz. Table 12 Operating modes MODE Start mode 1 Start mode 2
It should be noted that the crossover frequencies f3 and f4 are scaled with the overspeed factor `n' whereas the gains are not. 7.15.4 FIFO OVERFLOW
If FIFO overflow occurs during Play mode (e.g. as a result of motor rotational shock), the FIFO will be automatically reset to 50% and the audio interpolator will conceal as much as possible to minimize the effect of data loss.
DESCRIPTION The disc is accelerated by applying a positive voltage to the spindle motor. No decisions are involved and the PLL is reset. No disc speed information is available for the microcontroller. The disc is accelerated as in start mode 1, however the PLL will monitor the disc speed. When the disc reaches 75% of its nominal speed, the controller will switch to jump mode. The motor status signals selectable via register 2 are valid. Motor servo enabled but FIFO kept reset at 50%, integrator is held. The audio is muted but it is possible to read the subcode. It should be noted that in the CD-ROM modes the data, on EBU and the I2S-bus, is not muted. Similar to jump mode but motor integrator is kept at zero. It is used for long jumps where there is a large change in disc speed. FIFO released after resetting to 50% and the audio mute is released. Disc is braked by applying a negative voltage to the motor; no decisions are involved. The disc is braked as in stop mode 1 but the PLL will monitor the disc speed. As soon as the disc reaches 12% (or 6%, depending on the programmed brake percentage, via register E) of its nominal speed, the MOTSTOP status signal will go HIGH and switch the motor servo to off mode. Motor not steered.
Jump mode
Jump mode 1 Play mode Stop mode 1 Stop mode 2
Off mode
MGA362 - 2
G
f4
f3
BW
f
Fig.20 Motor servo mode diagram.
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CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
7.16 7.16.1 Servo part DIODE SIGNAL PROCESSING
SAA7824
The photo detector in conventional two-stage three-beam Compact Disc systems normally contains six discrete diodes. Four of these diodes (three for single foucault systems) carry the Central Aperture signal (CA) while the other two diodes (satellite diodes) carry the radial tracking information. The CA signals are summed into an HF signal for the decoder function and are also differentiated (after analog-to-digital conversion) to produce the low frequency focus control signals.
The low frequency content of the six (five if single Foucault) photo diode inputs are converted to digital Pulse Density Modulated (PDM) bitstreams by six Sigma-delta ADCs. These support a range of OPUs by interfacing to Voltage mode mechanisms and by having 16 selectable gain ranges in two sets, one set for D1-to-D4 and the other for R1 and R2.
Table 13 Shadow register settings to control diode voltage ranges SHADEN BITS 01 (bank 1) SHADOW REGISTER A signal magnitude control for diodes D1 to D4 (LF only) ADDRESS 1010 DATA 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 VOLTAGE (mV) 20 25 30 40 60 75 100 120 150 200 270 350 450 600 720 960 INITIAL - - - - - - - - - - - - - - - reset
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Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SHADOW REGISTER C signal magnitude control for diodes R1 and R2 (LF only)
SAA7824
SHADEN BITS 01 (bank 1)
ADDRESS 1100
DATA 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
VOLTAGE (mV) 20 25 30 40 60 75 100 120 150 200 270 350 450 600 720 960
INITIAL - - - - - - - - - - - - - - - reset
7.16.2
SIGNAL CONDITIONING
The digital codes retrieved from the ADCs are applied to logic circuitry to obtain the various control signals. The signals from the central aperture diodes are processed to obtain a normalised focus error signal: D1 - D2 D3 - D4 FE n = --------------------- - --------------------D1 + D2 D3 + D4 Where the detector set-up is assumed to be as shown in Fig.21. In the event of single Foucault focusing method, the signal conditioning can be switched under software control such that the signal processing is as follows: D1 - D2 FE n = 2 x --------------------D1 + D2 The error signal, FEn, is further processed by a Proportional Integral and Differential (PID) filter section. A Focus OK (FOK) flag is generated by the central aperture signal and an adjustable reference level. This signal is used to provide extra protection for the Track-Loss (TL) generation, the focus start-up procedure and the dropout detection.
The radial or tracking error signal is generated by the satellite detector signals R1 and R2. The radial error signal can be formulated as follows: REs = (R1 - R2) x re_gain + (R1 + R2) x re_offset. Where the index `s' indicates the automatic scaling operation which is performed on the radial error signal. This scaling is necessary to avoid non-optimum dynamic range usage in the digital representation and reduces the radial bandwidth spread. Furthermore, the radial error signal will be made free from offset during start-up of the disc. The four signals from the central aperture detectors, together with the satellite detector signals generate a Track Position signal (TPI) which can be formulated as follows: TPI = sign [(D1 + D2 + D3 + D4) - (R1 + R2) x sum_gain] Where the weighting factor sum_gain is generated internally by the SAA7824 during initialization.
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SAA7824
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SATELLITE DIODE R1
SATELLITE DIODE R1
SATELLITE DIODE R1
D1 D3 D2
D2 D4
D1 D3
D1 D2 D3 D4
SATELLITE DIODE R2
SATELLITE DIODE R2
SATELLITE DIODE R2
single Foucault
astigmatic focus
double Foucault
MBG422
Fig.21 Detector arrangement.
7.16.3
FOCUS SERVO SYSTEM
7.16.3.1
Focus start-up
Five initially loaded coefficients influence the start-up behaviour of the focus controller. The automatically generated triangular voltage can be influenced by 3 parameters; for height (ramp_height) and DC offset (ramp_offset) of the triangle and its steepness (ramp_incr). For protection against false focus point detections two parameters are available which are an absolute level on the CA signal (CA_start) and a level on the FEn signal (FE_start). When this CA level is reached the FOK signal becomes true. If the FOK signal is true and the level on the FEn signal is reached, the focus PID is enabled to switch-on when the next zero crossing is detected in the FEn signal.
These coefficients influence the integrating (foc_int), proportional (foc_lead_length, part of foc_parm3) and differentiating (foc_pole_lead, part of foc_parm1) action of the PID and a digital low-pass filter (foc_pole_noise, part of foc_parm2) following the PID. The fifth coefficient foc_gain influences the loop gain.
7.16.3.3
Dropout detection
This detector can be influenced by one parameter (CA_drop). The FOK signal will become false and the integrator of the PID will hold if the CA signal drops below this programmable absolute CA level. When the FOK signal becomes false it is assumed, initially, to be caused by a black dot.
7.16.3.4
Focus loss detection and fast restart
7.16.3.2
Focus position control loop
The focus control loop contains a digital PID controller which has 5 parameters that are available to the user.
Whenever FOK is false for longer than approximately 3 ms, it is assumed that the focus point is lost. A fast restart procedure is initiated which is capable of restarting the focus loop within 200 to 300 ms depending on the programmed coefficients of the microcontroller.
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7.16.3.5 Focus loop gain switching
SAA7824
The gain of the focus control loop (foc_gain) can be multiplied by a factor of 2 or divided by a factor of 2 during normal operation. The integrator value of the PID is corrected accordingly. The differentiating (foc_pole_lead) action of the PID can be switched at the same time as the gain switching is performed.
7.16.3.6
Focus automatic gain control loop
The loop gain of the focus control loop can be corrected automatically to eliminate tolerances in the focus loop. This gain control injects a signal into the loop which is used to correct the loop gain. Since this decreases the optimum performance, the gain control should only be activated for a short time (for example, when starting a new disc). 7.16.4 RADIAL SERVO SYSTEM
Both modes of S-curve extension make use of a track-count mechanism. In this mode, track counting results in an `automatic return-to-zero track', to avoid major disturbances in the audio output and providing improved shock resistance. The sledge is continuously controlled, or provided with step pulses to reduce power consumption using the filtered value of the radial PID output. Alternatively, the microcontroller can read the average voltage on the radial actuator and provide the sledge with step pulses to reduce power consumption. Filter coefficients of the continuous sledge control can be preset by the user.
7.16.4.4
Access
The access procedure is divided into two different modes (see Table 14), depending on the requested jump size. Table 14 Access modes ACCESS TYPE JUMP SIZE(1) ACCESS SPEED decreasing velocity maximum power to sledge(1)
7.16.4.1
Level initialization
During start-up an automatic adjustment procedure is activated to set the values of the radial error gain (re_gain), offset (re_offset) and satellite sum gain (sum_gain) for TPI level generation. The initialization procedure runs in a radial open loop situation and is 300 ms. This start-up time period may coincide with the last part of the motor start-up time period: * Automatic gain adjustment: as a result of this initialization the amplitude of the RE signal is adjusted to within 10% around the nominal RE amplitude * Offset adjustment: the additional offset in RE due to the limited accuracy of the start-up procedure is less than 50 nm * TPI level generation: the accuracy of the initialization procedure is such that the duty factor range of TPI becomes 0.4 < duty factor < 0.6 (default duty factor = TPI HIGH/TPI period).
Actuator jump 1 - brake_distance Sledge jump brake_distance -32768
Note 1. The microcontroller can be preset. The access procedure makes use of a track counting mechanism, a velocity signal based on a fixed number of tracks passed within a fixed time interval, a velocity set point calculated from the number of tracks to go and a user programmable parameter indicating the maximum sledge performance. If the number of tracks remaining is greater than the brake_distance then the sledge jump mode should be activated or, the actuator jump should be performed. The requested jump size together with the required sledge breaking distance at maximum access speed defines the brake_distance value. During the actuator jump mode, velocity control with a PI controller is used for the actuator. The sledge is then continuously controlled using the filtered value of the radial PID output. All filter parameters (for actuator and sledge) are user programmable.
7.16.4.2
Sledge control
The microcontroller can move the sledge in both directions via the steer sledge command.
7.16.4.3
Tracking control
The actuator is controlled using a PID loop filter with user defined coefficients and gain. For stable operation between the tracks, the S-curve is extended over 75% of the track. On request from the microcontroller, S-curve extension over 2.25 tracks is used, automatically changing to access control when exceeding those 2.25 tracks.
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In the sledge jump mode maximum power (user programmable) is applied to the sledge in the correct direction while the actuator becomes idle (the content of the actuator integrator leaks to zero just after the sledge jump mode is initiated). The actuator can be electronically damped during sledge jump. The gain of the damping loop is controlled via the hold_mult parameter. The fast track jumping circuitry can be enabled or disabled via the xtra_preset parameter.
SAA7824
3. Fast counting state: used in high velocity track jump situations. Highest obtainable velocity is the most important feature in this state. 7.16.6 TRACK COUNTING MODES
7.16.4.5
Radial automatic gain control loop
Fast counting mode is auto-selected for a track crossing speed above 1200 tracks/s. In this case the off-track counting decrements occur only for effect of the RP signal, and the direction of the jump is already known because the Slow counting mode occurs before going into Fast counting mode. When the Slow counting mode is selected, the maximum track crossing speed that can be reached is 12 kHz (providing that the maximum value for rad_pole_lead is used). In this case the direction of the jump is given by the phase shift between RP and TL (+90 degrees for outward jumps, -90 degrees for inward jumps). The number of pulses in the TL signal gives the number of tracks crossed. When the Fast counting mode is enabled, whenever the track crossing speed goes below 12 kHz, the counting mode is automatically changed to Slow. 7.16.7 DEFECT DETECTION
The loop gain of the radial control loop can be corrected automatically to eliminate tolerances in the radial loop. This gain control injects a signal into the loop which is used to correct the loop gain. Since this decreases the optimum performance, the gain control should only be activated for a short time (for example, when starting a new disc). This gain control differs from the level initialization. The level initialization should be performed first. The disadvantage of using the level initialization without the gain control is that only tolerances from the front-end are reduced. 7.16.5 OFF-TRACK COUNTING
The Track Position signal (TPI) is a flag which is used to indicate whether the radial spot is positioned on the track, with a margin of 0.25 of the track pitch. In combination with the Radial Polarity flag (RP) the relative spot position over the tracks can be determined. These signals can have uncertainties caused by: * Disc defects such as scratches and fingerprints * The HF information on the disc, which is considered as noise by the detector signals. In order to determine the spot position with sufficient accuracy, extra conditions are necessary to generate a Track Loss signal (TL) and an off-track counter value. These extra conditions influence the maximum speed and this implies that, internally, one of the following three counting states is selected: 1. Protected state: used in normal play situations. A good protection against false detection caused by disc defects is important in this state. 2. Slow counting state: used in low velocity track jump situations. In this state a fast response is important rather than the protection against disc defects (if the phase relationship between TL and RP of 0.5 radians is affected too much, the direction cannot then be determined accurately).
A defect detection circuit is incorporated into the SAA7824. If a defect is detected, the radial and focus error signals may be zeroed, resulting in better playability. The defect detector can be switched off, applied only to focus control or applied to both focus and radial controls under software control (part of foc_parm1). The defect detector (see Fig 22) has programmable set points selectable by the parameter defect_parm. 7.16.8 OFF-TRACK DETECTION
During active radial tracking, off-track detection has been realised by continuously monitoring the off-track counter value. The off-track flag becomes valid whenever the off-track counter value is not equal to zero. Depending on the type of extended S-curve, the off-track counter is reset after 0.75 extend or at the original track in the 2.25 track extend mode.
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CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SAA7824
handbook, full pagewidth
sat1
+ -
DECIMATION FILTER
FAST FILTER
SLOW FILTER
DEFECT GENERATION
PROGRAMMABLE HOLD-OFF
defect output
sat2
MBG421
Fig.22 Block diagram of the defect detector.
7.16.9
HIGH-LEVEL FEATURES
7.16.9.1
Interrupt mechanism and STATUS pin
The STATUS pin is an output which can be configured by decoder register 7 and new shadow register C (bank 3) for one of three different modes of operation. These are: * Output the interrupt signal generated by the servo part (it should be noted that the selection of this mode will override all other modes) * Output the decoder status bit (active LOW) selected by decoder register 2 (only available in 4-wire bus mode) * Output DC offset information (it should be noted that this mode is used in conjunction with the decoder status mode; see Section 7.5). Eight signals from the interrupt status register are selectable from the servo part via the interrupt_mask parameter. The interrupt is reset by sending the read high-level status command. The 8 signals are as follows: * Focus lost: dropout of longer than 3 ms * Subcode ready * Subcode absolute seconds changed * Subcode discontinuity detected: new subcode time before previous subcode time, or more than 10 frames later than previous subcode time * Radial error: during radial on-track, no new subcode frame occurs within the time defined by the `playwatchtime' parameter; during radial jump, less than 4 tracks have been crossed during the time defined by the `jumpwatchtime' parameter * Autosequencer state change * Autosequencer error * Subcode interface blocked: the internal decoder interface is being used.
It should be noted that if the STATUS pin is configured to output decoder status information [decoder register 7 = XX10 and new shadow register C (bank 3) = X00X] and either the microcontroller writes a different value to decoder register 2 or the decoder interface is enabled then the STATUS output will change.
7.16.9.2
Decoder interface
The decoder interface allows decoder and shadow registers to be programmed and subcode Q-channel data to be read via servo commands. The interface is enabled or disabled by the preset latch command (and the xtra_preset parameter).
7.16.9.3
Automatic error handling
Three Watchdogs are present: * Focus: detects focus dropout of longer than 3 ms, sets focus lost interrupt, switches off radial and sledge servos and disables the drive-to-disc motor * Radial play: started when radial servo is in on-track mode and a first subcode frame is found; detects when the maximum time between two subcode frames exceeds the time set by the playwatchtime parameter; it then sets the radial error interrupt, switches radial and sledge servos off and puts the disc motor into jump mode * Radial jump: active when radial servo is in long jump or short jump modes; detects when the off-track counter value decreases by less than 4 tracks between two readings (the time interval is set by the jumpwatchtime parameter); it then sets the radial jump error, switches radial and sledge servos off to cancel jump. The focus Watchdog is always active, the radial Watchdogs are selectable via the radcontrol parameter.
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7.16.9.4 Automatic sequencers and timer interrupts
SAA7824
Two automatic sequencers are implemented (and must be initialized after Power-on): * Auto-start sequencer: controls the start-up of focus, radial and motor * Auto-stop sequencer: brakes the disc and shuts down the servos. When the automatic sequencers are not used it is possible to generate timer interrupts, defined by the time_parameter coefficient.
During reset (i.e. RESET pin is held LOW) the RA, FO and SL pins are high-impedance. At all other times, when the laser is switched off, the RA and FO pins output a 2 MHz 50% duty factor signal. 7.16.11 LASER INTERFACE The laser diode pre-amplifier function is built into the SAA7824 and is illustrated in Fig.24. The current can be regulated, up to 120 mA in four steps ranging from 58% up to full power. New shadow register A (bank 2) and new shadow register 3 (bank 3) are used to select the step values. The voltage derived from the monitor diode is maintained at a steady state by the laser drive circuitry, regulating the current through the laser diode. The type of monitor diode being used (150 mV or 180 mV) must be selected by new shadow register 7 (bank 2) (reset state = 150 mV). The laser can be switched on or off by the xtra_preset parameter; it is automatically driven if the focus control loop is active.
7.16.9.5
High-level status
The read high-level status command can be used to obtain the interrupt, decoder, autosequencer status registers and the motor start time. Use of the read high-level status command clears the interrupt status register, and re-enables the subcode read via a servo command. 7.16.10 DRIVER INTERFACE The control signals (pins RA, FO and SL) for the mechanism actuators are pulse density modulated. The modulating frequency can be set to either 1.0584 or 2.1168 MHz; controlled via the xtra_preset parameter. An analog representation of the output signals can be achieved by connecting a 1st-order low-pass filter to the outputs.
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7.17 Microcontroller interface
SAA7824
Communication on the microcontroller interface can be set-up in three different modes: * 4-wire bus mode: where: - SCL = serial clock - SDA = serial data - RAB = R/W control and data strobe (active HIGH) for writing to decoder registers 0 to F, reading status bit selected via decoder register 2 and reading Q-channel subcode - SILD = R/W control and data strobe (active LOW) for servo commands * 3-wire bus mode: where: - SCL = serial clock - SDA = serial data - RAB = not used, pulled LOW - SILD = R/W control and data strobe (active LOW) for servo commands
* I2C-bus mode: I2C-bus protocol where the SAA7824 behaves as slave device, activated by setting RAB = HIGH and SILD = LOW where: - I2C-bus slave address (write mode) = 30H - I2C-bus slave address (read mode) = 31H - Maximum data transfer rate = 400 kbits/s. It should be noted that when using the I2C-bus mode, only servo commands can be used. Therefore, writing to decoder registers 0 to F, reading decoder status and reading Q-channel subcode data must be performed by servo commands. The 3-wire mode is very similar to the 4-wire mode, except that all communication to the decoder is via the servo. Communication to the servo uses the same hardware protocol and timing as the 4-wire mode. Extra servo commands exist for read and write access to the decoder via the internal decoder interface. The internal interface must be enabled by using the xtra_preset command. RAB is not used and must be tied LOW; see Fig.23
handbook, halfpage
MICROCONTROLLER INTERFACE (DECODER)
MICROCONTROLLER INTERFACE
SAA7824
RAB = LOW SDA SCL SILD
MDB502
Fig.23 Microcontroller interface for the 3-wire mode.
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SAA7824
handbook, full pagewidth
floating reference
VDDA
laser power control [register A (bank 2) and register 3 (bank 3)] mech_sel
error amplifier
power amplifier
gm
gm
power-down or laser off VSENSE MONITOR EXFILTER LASER
47 nF monitor diode
laser diode
MBL442
Fig.24 Simplified block diagram of the laser driver.
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CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
7.17.1 MICROCONTROLLER INTERFACE (4-WIRE BUS MODE) * V1: follows input on pin V1 * V2: follows input on pin V2
SAA7824
7.17.1.1
Writing data to registers 0 to F
The sixteen 4-bit programmable configuration registers, 0 to F (see Table 15), can be written to via the microcontroller interface using the protocol shown in Fig.25. It should be noted that SILD must be held HIGH; A3 to A0 identifies the register number and D3 to D0 is the data. The data is latched into the register on the LOW-to-HIGH transition of RAB.
* MOTOR-OV: HIGH if the motor servo output stage saturates. The status read protocol is illustrated in Fig.27. It should be noted that SILD must be held HIGH.
7.17.1.5
Reading Q-channel subcode
7.17.1.2
Writing repeated data to registers 0 to F
The same data can be repeated several times (e.g. for a fade function) by applying extra RAB pulses as shown in Fig.26. It should be noted that SCL must stay HIGH between RAB pulses.
To read the Q-channel subcode direct in the 4-wire bus mode, the SUBQREADY-I signal should be selected as the status signal. The subcode read protocol is illustrated in Fig.28. It should be noted that SILD must be held HIGH; after subcode read starts, the microcontroller may take as long as it wants to terminate the read operation. When enough subcode has been read (1 to 96 bits), the reading can be terminated by pulling RAB LOW. Alternatively, the Q-channel subcode can be read using a servo command as follows: * Use the read high-level status command to monitor the subcode ready signal * Send the read subcode command and read the required number of bytes (up to 12) * Send the read high-level status command; to re-enable the decoder interface.
7.17.1.3
Multiple writes to the new shadow registers
Some of the new shadow registers are a multiple of four bits in length and require a number of write operations to fill them up; see Section 7.17.5. They must be completely filled before writing to another register, otherwise unpredictable behaviour may result. The protocol for writing to these registers is exactly the same as the decoder registers; see Fig.25. The write command must be executed multiple times with the same address content. The first four bits of data in a sequence of write commands represent the most significant nibble of the register, while the last four represent the least significant nibble. The data content can change from one write to the next without consequence.
7.17.1.6
Behaviour of the SUBQREADY-I signal
7.17.1.4
Reading decoder status information on SDA
When the CRC of the Q-channel word is good, and no subcode is being read, the SUBQREADY-I status signal will react as illustrated in Fig.29. When the CRC is good and the subcode is being read, the timing in Fig.30 applies. If t1 (SUBQREADY-I status LOW to end of subcode read) is below 2.6/n ms, then t2 = 13.1/n ms (i.e. the microcontroller can read all subcode frames if it completes the read operation within 2.6/n ms after the subcode is ready). If these criteria are not met, it is only possible to guarantee that t3 will be below 26.2/n ms (approximately). If subcode frames with failed CRCs are present, the t2 and t3 times will be increased by 13.1/n ms for each defective subcode frame. It should be noted that in the lock-to-disc mode `n' is replaced by `d', which is the disc speed factor.
There are several internal status signals, selected via register 2, which can be made available on the SDA line: * SUBQREADY-I: LOW if new subcode word is ready in Q-channel register * MOTSTART1: HIGH if motor is turning at 75% or more of nominal speed * MOTSTART2: HIGH if motor is turning at 50% or more of nominal speed * MOTSTOP: HIGH if motor is turning at 12% or less of nominal speed; can be set to indicate 6% or less (instead of 12% or less) via register E * PLL lock: HIGH if sync coincidence signals are found
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7.17.1.7 Write servo commands
SAA7824
A write data command is used to transfer data (a number of bytes) from the microcontroller, using the protocol illustrated in Fig.31. The first of these bytes is the command byte and the following are data bytes; the number (between 1 and 7) depends on the command byte. It should be noted that RAB must be held LOW; the command or data is interpreted by the SAA7824 after the HIGH-to-LOW transition of SILD; there must be a minimum time of 70 s between SILD pulses.
The sequence for a write data command (that requires 3 data bytes) is as follows: 1. Send START condition. 2. Send address 30H (write). 3. Write command byte. 4. Write data byte 1. 5. Write data byte 2. 6. Write data byte 3. 7. Send STOP condition. It should be noted that more than one command can be sent in one write sequence. The sequence for a read data command (that reads 2 data bytes) is as follows: 1. Send START condition. 2. Send address 30H (write). 3. Write command byte. 4. Send STOP condition. 5. Send START condition. 6. Send address 31H (read). 7. Read data byte 1. 8. Read data byte 2. 9. Send STOP condition. It should be noted that the timing constraints specified for the read and write servo commands must still be adhered to.
7.17.1.8
Writing repeated data in servo commands
The same data byte can be repeated by applying extra SILD pulses as illustrated in Fig.32. SCL must be HIGH between the SILD pulses.
7.17.1.9
Read servo commands
A read data command is used to transfer data (status information) to the microcontroller, using the protocol shown in Fig.33. The first byte written determines the type of command. After this byte a variable number of bytes can be read. It should be noted that RAB must be held LOW; after the end of the command byte (LOW-to-HIGH transition on SILD) there must be a delay of 70 s before data can be read (i.e. the next HIGH-to-LOW transition on SILD) and there must be a minimum time of 70 s between SILD pulses. 7.17.2 MICROCONTROLLER INTERFACE (I2C-BUS MODE)
Bytes are transferred over the interface in groups (i.e. servo commands) of which there are two types: write data commands and read data commands.
handbook, full pagewidth RAB
(microcontroller)
SCL (microcontroller) SDA (microcontroller) SDA (SAA782X) A3 A2 A1 A0 D3 D2 D1 D0
high-impedance
MBL445
Fig.25 Microcontroller write protocol for registers 0 to F.
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SAA7824
RAB handbook, full pagewidth
(microcontroller)
SCL (microcontroller) SDA (microcontroller) SDA (SAA782X) A3 A2 A1 A0 D3 D2 D1 D0
high-impedance
MBL446
Fig.26 Microcontroller write protocol for registers 0 to F (repeat mode).
handbook, full pagewidthRAB
(microcontroller)
SCL (microcontroller) SDA (microcontroller) SDA (SAA782X)
high-impedance STATUS
MBL443
Fig.27 Microcontroller read protocol for decoder status on SDA.
RAB handbook, full pagewidth
(microcontroller)
SCL (microcontroller) SDA (SAA782X) STATUS CRC OK Q1 Q2 Q3 Qn-2 Qn-1 Qn
MBL444
Fig.28 Microcontroller protocol for reading Q-channel subcode.
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SAA7824
handbook, full pagewidth
RAB (microcontroller)
SCL (microcontroller) SDA (SAA782X) high impedance CRC OK CRC OK
10.8/n ms
15.4/n ms 2.3/n ms
MBL447
READ start allowed
Fig.29 SUBQREADY-I status timing when no subcode is read.
handbook, full pagewidth
t2 t1 t3
RAB (microcontroller) SCL (microcontroller) SDA (SAA782X) Q1 Q2 Q3 Qn
MBL448
Fig.30 SUBQREADY-I status timing when subcode is read.
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SAA7824
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SILD (microcontroller) SCL (microcontroller) SDA (microcontroller) SDA (SAA782X) high-impedance microcontroller write (one byte: command or data) SILD (microcontroller) SDA (microcontroller) COMMAND DATA1 DATA2 DATA3
MBL449
D7
D6
D5
D4
D3
D2
D1
D0
command or data byte
microcontroller write (full command)
Fig.31 Microcontroller protocol for write servo commands.
handbook, full pagewidth
SILD (microcontroller) SDA (microcontroller) COMMAND DATA1
MBG413
microcontroller write (full command)
Fig.32 Microcontroller protocol for repeated data in write servo commands.
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SAA7824
handbook, full pagewidth
SILD (microcontroller) SCL (microcontroller) SD (SAA782X) D7 D6 D5 D4 D3 data byte microcontroller read (one data byte) SILD (microcontroller) SD (SAA782X) SDA (microcontroller) COMMAND
MBL450
D2
D1
D0
DATA1
DATA2
DATA3
microcontroller read (full command)
Fig.33 Microcontroller protocol for read servo commands.
7.17.3
DECODER AND SHADOW REGISTERS
To maintain compatibility with the SAA732x series, decoder registers 0 to F and the shadow registers are largely unchanged. However, to control the extra functionality of SAA7824, the shadow registers have been extended to include new shadow registers. All shadow registers are accessed by using the two LSBs (bits 0 and 1) of decoder register F. These bits are called SHADEN1 and SHADEN2 respectively. These bits are decoded according to Table 15. This two bit encoding allows the use of three shadow register banks; bank 1 (SAA732X shadow registers), and banks 2 and 3 (new shadow registers). Only the four addresses 3, 7, A and C are implemented in any one bank. Any other addresses sent while accessing any of the shadow register banks are invalid and have no effect.
When SHADEN1 and SHADEN2 are both set to logic 0 (decoder register F set to XX00) all subsequent addresses are decoded by the main decoder registers again. Access to decoder register F is always enabled so that SHADEN1 and SHADEN2 can be set or reset as required. The SHADEN bits and subsequent shadow registers are programmed identically to the main decoder registers, i.e. they can be directly programmed when using the SAA7824 in 4-wire mode or programmed via the servo interface when using 3-wire or I2C-bus modes. The main decoder registers are given in Table 16 and the shadow registers in Table 18. Details of the new shadow registers can be found in Tables 19 to 22.
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Table 15 Shadow register accessibility SHADEN2 0 0 1 1 7.17.4 SHADEN1 0 1 0 1 FUNCTION access decoder registers 0 to F access SAA732X shadow registers (bank 1) access new shadow registers (bank 2) access new shadow registers (bank 3)
SAA7824
INITIAL reset - - -
SUMMARY OF FUNCTIONS CONTROLLED BY DECODER REGISTERS 0 TO F
Table 16 Registers 0 to F REGISTER 0 (Fade and attenuation) ADDRESS 0000 DATA X000 X010 X001 X100 X101 0 EBU mute (for M1 version only) 1 (Motor mode) 0001 0XXX 1XXX mute attenuate full-scale step-down step-up EBU mute inactive EBU mute active FUNCTION INITIAL(1) reset - - - - reset -
X000 X001 X010 X011 X100 X101 X111 X110 1XXX 0XXX
motor off mode motor stop mode 1 motor stop mode 2 motor start mode 1 motor start mode 2 motor jump mode motor play mode motor jump mode 1 anti-windup active anti-windup off status = SUBQREADY-I status = MOTSTART1 status = MOTSTART2 status = MOTSTOP status = PLL lock status = V1 status = V2 status = MOTOR-OV status = FIFO overflow status = shock detect status = latched shock detect status = latched shock detect reset
reset - - - - - - - - reset reset - - - - - - - - - - -
2 (Status control)
0010
0000 0001 0010 0011 0100 0101 0110 0111
unavailable via the I2C-bus or 3-wire mode
1000 1001 1010 1011
2003 Oct 01
44
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
REGISTER 3 (DAC output) ADDRESS 0011 DATA 1010 1011 1100 1111 1110 0000 0011 0010 0100 0111 0110 4 (Motor gain) 0100 0000 0001 0010 0011 0100 0101 0110 0111 5 (Motor bandwidth) 0101 XX00 XX01 XX10 XX11 00XX 01XX 10XX 6 (Motor output configuration) 0110 XX00 XX01 XX10 XX11 00XX 01XX 10XX 11XX FUNCTION I2S-bus; CD-ROM mode EIAJ; CD-ROM mode I2S-bus; 18-bit; 4fs mode I2S-bus; 18-bit; 2fs mode I2S-bus; 16-bit; fs mode EIAJ; 16-bit; 4fs EIAJ; 16-bit; 2fs EIAJ; 16-bit; fs EIAJ; 18-bit; 4fs EIAJ; 18-bit; 2fs EIAJ; 18-bit; fs motor gain G = 3.2 motor gain G = 4.0 motor gain G = 6.4 motor gain G = 8.0 motor gain G = 12.8 motor gain G = 16.0 motor gain G = 25.6 motor gain G = 32.0 motor f4 = 0.5 x n Hz motor f4 = 0.7 x n Hz motor f4 = 1.4 x n Hz motor f4 = 2.8 x n Hz motor f3 = 0.85 x n Hz motor f3 = 1.71 x n Hz motor f3 = 3.42 x n Hz motor power maximum 37% motor power maximum 50% motor power maximum 75% motor power maximum 100% MOTO1, MOTO2 pins 3-state motor PWM mode motor PDM mode motor CDV mode
SAA7824
INITIAL(1) - - reset - - - - - - - - reset - - - - - - - reset - - - reset - - reset - - - reset - - -
2003 Oct 01
45
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
REGISTER 7 (DAC output and STATUS pin control) ADDRESS 0111 DATA XX00 XX10 FUNCTION interrupt signal from servo only at STATUS pin status bit from decoder status register or DC offset information at STATUS pin [see also new shadow register C (bank 3)] DAC data normal value DAC data inverted value left channel first at DAC (WCLK normal) right channel first at DAC (WCLK inverted) see Table 16
SAA7824
INITIAL(1) reset -
X0XX X1XX 0XXX 1XXX 8 (PLL loop filter bandwidth) 9 (PLL equalization) 1001 0011 0001 0010 0100 0101 A (EBU output) 1010 XX0X XX1X X0X0 X0X1 X1X0 X1X1 0XXX 1XXX B (speed control) 1011 X000 X010 X011 00XX 10XX C (versatile pins interface and KILL function) 1100 XXX1 XXX0 XX0X XX1X 00XX 01XX EBU mute mode (for M1 version only) 0XXX 1XXX
reset - reset - -
PLL loop filter equalization PLL 30 ns over-equalization PLL 15 ns over-equalization PLL 15 ns under-equalization PLL 30 ns under-equalization EBU data before concealment EBU data after concealment and fade Level II clock accuracy (<1000 ppm) Level I clock accuracy (<50 ppm) Level III clock accuracy (>1000 ppm) EBU off - output LOW flags in EBU off flags in EBU on standby 1: `CD-STOP' mode standby 2: `CD-PAUSE' mode operating mode single-speed mode double-speed mode external off-track signal input at V1 internal off-track signal used (V1 may be read via status) stereo KILL mono KILL V3 = 0 V3 = 1 mute type = soft mute audio; only available at 1x speed mute type = ROM hard mute; available at 1x, 2x and 4x speed
reset - - - - - reset reset - - - reset - reset - - reset - - reset - reset reset - reset -
2003 Oct 01
46
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
REGISTER D (versatile pins interface) ADDRESS 1101 DATA 0000 XX01 XX10 XX11 01XX 10XX 11XX E 1110 XXX0 XXX1 XX0X XX1X X0XX X1XX 0XXX 1XXX F (subcode interface and shadow register enable) 1111 X0XX X1XX 0XXX 1XXX XX00 FUNCTION 4-line motor (using V4 and V5) Q-to-W subcode at V4 V4 = 0 V4 = 1 de-emphasis signal at V5, no internal de-emphasis filter V5 = 0 V5 = 1 motor brakes to 12% motor brakes to 6% lock-to-disc mode disabled lock-to-disc mode enabled audio features disabled audio features enabled quad-speed mode disabled quad-speed mode enabled subcode interface off subcode interface on 4-wire subcode 3-wire subcode SHADEN bits = 00; shadow registers not enabled; addresses will be decoded by main decoder registers SHADEN bits = 01; SAA732X shadow registers (bank 1) enabled; all subsequent addresses will be decoded by shadow register (bank 1), not decoder registers SHADEN bits = 10; new shadow registers (bank 2) enabled; all subsequent addresses will be decoded by shadow register (bank 2) SHADEN bits = 11; new shadow registers (bank 3) enabled; all subsequent addresses will be decoded by shadow register (bank 3)
SAA7824
INITIAL(1) - - - reset - - reset reset - reset - - reset reset - reset - reset - reset
XX01
-
XX10
-
XX11
-
Note 1. The initial column shows the Power-on reset state.
2003 Oct 01
47
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 17 Loop filter bandwidth FUNCTION REGISTER ADDRESS DATA LOOP BANDWIDTH (Hz) 1640 x n 3279 x n 6560 x n 1640 x n 3279 x n 6560 x n 1640 x n 3279 x n 6560 x n 1640 x n 3279 x n 6560 x n INTERNAL BANDWIDTH (Hz) 525 x n 263 x n 131 x n 1050 x n 525 x n 263 x n 2101 x n 1050 x n 525 x n 4200 x n 2101 x n 1050 x n LOW-PASS BANDWIDTH (Hz) 8400 x n 16800 x n 33600 x n 8400 x n 16800 x n 33600 x n 8400 x n 16800 x n 33600 x n 8400 x n 16800 x n 33600 x n
SAA7824
INITIAL(1)
8 (PLL loop filter bandwidth)
1000
0000 0001 0010 0100 0101 0110 1000 1001 1010 1100 1101 1110
- - - - - - - reset - - - -
Note 1. The initial column shows the Power-on reset state. 7.17.5 SUMMARY OF FUNCTIONS CONTROLLED BY SHADOW REGISTERS
Table 18 Bank 1 shadow register settings (single write) SHADEN BITS 01 (bank 1) SHADOW REGISTER 3 control of versatile and clock pins ADDRESS 0011 DATA XX00 XX01 X0XX X1XX 0XXX 1XXX 7 control of onboard DAC 7 EBU mute bypass control (for M1 version only) 0111 0000 FUNCTION select CLK4 on CLK4/12 output select CLK12 on CLK4/12 output enable CLK16 output pin set CLK16 output pin to high-impedance set V3 output pin to high-impedance enable V3 output pin use external DAC or route audio data back into onboard DAC (loopback mode) route audio data directly into onboard DAC (non-loopback mode) EBU mute function not bypassed EBU mute function bypassed INITIAL reset - reset - reset - reset
0010 XXX0 XXX1
- reset -
2003 Oct 01
48
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SHADEN BITS 01 (bank 1) SHADOW REGISTER A signal magnitude control for diodes D1 to D4 (LF only)
SAA7824
ADDRESS 1010
DATA 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
FUNCTION voltage mode: 20 mV voltage mode: 25 mV voltage mode: 30 mV voltage mode: 40 mV voltage mode: 60 mV voltage mode: 75 mV voltage mode: 100 mV voltage mode: 120 mV voltage mode: 150 mV voltage mode: 200 mV voltage mode: 270 mV voltage mode: 350 mV voltage mode: 450 mV voltage mode: 600 mV voltage mode: 720 mV voltage mode: 960 mV voltage mode: 20 mV voltage mode: 25 mV voltage mode: 30 mV voltage mode: 40 mV voltage mode: 60 mV voltage mode: 75 mV voltage mode: 100 mV voltage mode: 120 mV voltage mode: 150 mV voltage mode: 200 mV voltage mode: 270 mV voltage mode: 350 mV voltage mode: 450 mV voltage mode: 600 mV voltage mode: 720 mV voltage mode: 960 mV
INITIAL - - - - - - - - - - - - - - - reset - - - - - - - - - - - - - - - reset
01 (bank 1)
C signal magnitude control for diodes R1 and R2 (LF only)
1100
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
2003 Oct 01
49
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 19 Bank 2 new shadow register settings (single write) SHADEN BITS 10 (bank 2) SHADOW REGISTER 3 Power-down control ADDRESS 0011 DATA XXX0 XXX1 XX0X XX1X X0XX X1XX 3 DAC output mode 7 0111 mechanism and voltage reference selection 0XXX 1XXX XX10 FUNCTION analog front-end active analog front-end powered down buffer amplifier on buffer amplifier off (power saving) DAC active DAC powered down normal mode current mode (bypass internal I-to-V converters) voltage mechanism: 1.65 x V DDA ------------------------------3.3 V Voltage mechanism: 2.5 x V DDA ---------------------------3.3 V 150 mV mechanism 180 mV mechanism flag all data (CRC pass and fail) flag only data that passes the CRC
SAA7824
INITIAL reset - reset - reset - reset - reset
XX11
-
X0XX X1XX 7 CD-text control 0XXX 1XXX
reset - reset -
2003 Oct 01
50
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SHADEN BITS 10 (bank 2) SHADOW REGISTER A laser power control 1
SAA7824
ADDRESS 1010
DATA XXX0
FUNCTION approximately 58% (laser power control 2 = 0) approximately 72% (laser power control 2 = 1) see shadow register 3 (bank 3)
INITIAL reset
XXX1
approximately 86% (laser power control 2 = 0) approximately 100% (laser power control 2 = 1) see shadow register 3 (bank 3)
-
A clock source A KILL control
XX0X XX1X X0XX X1XX 0XXX 1XXX
bypass PLL (external clock source) select and enable PLL disable silence injection enable silence injection internal KILL loop-back KILL settling time = 354 s settling time = 1 ms settling time = 2 ms settling time = 10 ms no dither selected AC dither only DC dither only AC and DC dither selected
- reset reset - reset - reset - - - - - - reset
C DC offset measurement times C upsampler dither selection
1100
XX00 XX01 XX10 XX11 00XX 01XX 10XX 11XX
2003 Oct 01
51
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 20 Bank 3 new shadow register settings (single write) SHADEN BITS 11 (bank 3) SHADOW REGISTER 3 diode selection for DC offset measurement ADDRESS 0011 DATA X000 X001 X010 X011 X100 X101 X110 X111 3 laser power control 2 0XXX FUNCTION select D1 select D1 select D2 select D3 select D4 select R1 select R2 select D1 60% (laser power control 1 = 0) 87% (laser power control 1 = 1) see shadow register A (bank 2) 1XXX 73% (laser power control 1 = 0) 100% (laser power control 1 = 1) see shadow register A (bank 2) C enable equalizer C STATUS pin control 1100 XXX0 XXX1 000X equalizer disabled and powered-down equalizer enabled STATUS pin outputs decoder status register information STATUS pin outputs DC offset ready flag STATUS pin outputs DC offset value
SAA7824
INITIAL reset - - - - - - - reset
-
reset - reset
001X 010X
- -
Table 21 Bank 3 new shadow register settings (multiple write) SHADEN BITS 11 (bank 3) SHADOW REGISTER 7 DC cancellation levels A analog FE control Note 1. Register elements are described in Tables 26 and 27. 2003 Oct 01 52 ADDRESS 0111 SIZE (DATA NIBBLES) 9 REGISTER ELEMENTS(1)
1010
4
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 22 Multiple write register element description SHADOW REGISTER 7 (bank 3) ELEMENT NAME A (bank 3) Table 23 HF gain DATA 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DESCRIPTION voltage mode = 1.11 V voltage mode = 952 mV voltage mode = 588 mV voltage mode = 392 mV voltage mode = 1.11 V voltage mode = 952 mV voltage mode = 588 mV voltage mode = 392 mV voltage mode = 303 mV voltage mode = 200 mV voltage mode = 157 mV voltage mode = 107 mV voltage mode = 79 mV voltage mode = 54 mV voltage mode = 39 mV voltage mode = 27 mV BIT NUMBERS <5:0> <11:6> <17:12> <23:18> <29:24> <35:30> <3:0> <7:4> <9:8> <15:10> DESCRIPTION
SAA7824
DC offset level for D1 (reset value = 000000) DC offset level for D2 (reset value = 000000) DC offset level for D3 (reset value = 000000) DC offset level for D4 (reset value = 000000) DC offset level for R1 (reset value = 000000) DC offset level for R2 (reset value = 000000) see Table 23 see Table 24 equaliser operating speed: 00 = 1x (reset); 01 = 2x; 10 = 4x see Table 25 Table 24 Slicer threshold tracking slew rate (ISlice code to current conversion) DATA 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CURRENT (A) 10 (reset) 10 20 30 50 60 70 80 100 110 120 130 150 160 170 180
2003 Oct 01
53
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 25 High-pass filter frequency cut-off level (lowest roll-off) DATA 000000 010000 001000 011000 000100 010100 001100 000010 010010 001010 011010 000110 010110 001110 000001 010001 001001 011001 000101 010101 001101 000011 010011 001011 011011 000111 010111 001111 40 30 20 NOMINAL FREQUENCY (kHz) 10 PERCENTAGE DEVIATION -37.5% -28.2% -17.6% -9.2% 0% +8.6% +18% -37.5% -28.2% -17.6% -9.2% 0% +8.6% +18% -37.5% -28.2% -17.6% -9.2% 0% +8.6% +18% -37.5% -28.2% -17.6% -9.2% 0% +8.6% +18%
SAA7824
ACTUAL FREQUENCY (kHz) 6.367 (reset) 7.31 8.395 9.247 10.186 11.066 12.023 12.706 14.588 16.520 18.45 20.324 22.080 23.988 18.967 21.777 24.660 27.542 30.339 32.961 35.318 25.003 29.107 32.961 36.307 39.994 43.451 47.206
2003 Oct 01
54
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
7.17.6 SUMMARY OF SERVO COMMANDS
SAA7824
A list of the servo commands is given in Table 26. These are fully compatible with the SAA732X. Table 26 Servo commands COMMANDS Write commands Write_focus_coefs1 Write_focus_coefs2 Write_focus_command Focus_gain_up Focus_gain_down Write_radial coefs 17H 27H 33H 42H 62H 57H 7 7 3 2 2 7 `1CH' `3CH' CODE BYTES PARAMETERS
Preset_Latch Radial_off Radial_init Short_jump Long_jump Steer_sledge Preset_init Write_decoder_reg(1) Write_parameter Read commands Read_Q_subcode(1)(2) Read_status Read_hilevel_status(3) Read_aux_status Notes
81H C1H C1H C3H C5H B1H 93H D1H A2H
1 1 1 3 5 1 3 1 2
0H 70H E0H F0H
up to 12 up to 5 up to 4 up to 3

1. These commands are only available when the decoder interface is enabled. 2. and bytes are clocked out LSB first. 3. Decoder status flag information in, is only valid when the internal decoder interface is enabled.
2003 Oct 01
55
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
7.17.7 SUMMARY OF SERVO COMMAND PARAMETERS
SAA7824
Table 27 Servo command parameters PARAMETER foc_parm_1 foc_parm_2 foc_parm_3 foc_int foc_gain CA_drop ramp_offset ramp_height ramp_incr FE_start rad_parm_play rad_pole_noise rad_length_lead rad_int rad_gain rad_parm_jump vel_parm1 vel_parm2 speed_threshold hold_mult brake_dist_max sledge_long_brake sledge_Umax sledge_level sledge_parm_1 sledge_parm_2 RAM ADDRESS - - - 14H 15H 12H 16H 18H - 19H 28H 29H 1CH 1EH 2AH 27H 1FH 32H 48H 49H 21H 58H - - 36H 17H AFFECTS focus PID focus PID focus PID focus PID focus PID focus PID focus ramp focus ramp focus ramp focus ramp radial PID radial PID radial PID radial PID radial PID radial jump radial jump radial jump radial jump radial jump radial jump radial jump sledge sledge sledge sledge POR VALUE - - - - 70H - - - - - - - - - 70H - - - - 00H - FFH - - - - DETERMINES end of focus lead defect detector enabling focus low-pass focus error normalizing focus lead length minimum light level focus integrator crossover frequency focus PID loop gain sensitivity of dropout detector asymmetry of focus ramp peak-to-peak value of ramp voltage slope of ramp voltage minimum value of focus error end of radial lead radial low-pass length of radial lead radial integrator crossover frequency radial loop gain filter during jump PI controller crossover frequencies jump pre-defined profile maximum speed in fastrad mode electronic damping sledge bandwidth during jump maximum sledge distance allowed in fast actuator steered mode brake distance of sledge voltage on sledge during long jump voltage on sledge when steered sledge integrator crossover frequency sledge low-pass frequencies sledge gain sledge operation mode sledge_pulse1 sledge_pulse2 defect_parm playwatchtime jumpwatchtime 2003 Oct 01 46H 64H - 54H 57H pulsed sledge pulsed sledge defect detector Watchdog Watchdog 56 - - - - - pulse width pulse height defect detector setting radial on-track Watchdog time radial jump Watchdog time-out
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
RAM ADDRESS 59H - 4AH
SAA7824
PARAMETER radcontrol chip_init xtra_preset
AFFECTS Watchdog set-up set-up
POR VALUE - - 38H
DETERMINES enable/disable automatic radial off feature enable/disable decoder interface laser on/off RA, FO and SL PDM modulating frequency fast jumping circuit on/off
cd6cmd interrupt_mask seq_control focus_start_time motor_start_time1 motor_start_time2 radial_init_time brake_time RadCmdByte osc_inc phase_shift level1 level2 agc_gain
4DH 53H 42H 5EH 5FH 60H 61H 62H 63H 68H 67H 69H 6AH 6CH
decoder interface STATUS pin autosequencer autosequencer autosequencer autosequencer autosequencer autosequencer autosequencer focus/radial AGC focus/radial AGC focus/radial AGC focus/radial AGC focus/radial AGC
- - - - - - - - - - - - - - -
decoder part commands enabled interrupts autosequencer control focus start time motor start 1 time motor start 2 time radial initialization time brake time radial command byte AGC control frequency of injected signal phase shift of injected signal amplitude of signal injected amplitude of signal injected focus/radial gain
2003 Oct 01
57
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
8 SUMMARY OF SERVO COMMAND PARAMETERS VALUES
SAA7824
Table 29 foc_parm2 parameter: focus low-pass start frequency, focusing system foc_parm2 foc_pole_noise value (binary) xxx1 1100 xxx1 1000 xxx0 0000 xxx0 1000 xxx0 1100 xxx1 1101 xxx1 1001 xxx0 0001 xxx0 1001 xxx0 1101 xxx1 1110 xxx1 1010 xxx0 0010 xxx0 1010 xxx0 1110 xxx1 1111 xxx1 1011 xxx0 0011 xxx0 1011 detector_arr xx1x xxxx xx0x xxxx Focus low-pass start frequency f4 kHz 3.90 4.55 5.19 5.82 6.46 7.72 8.98 10.22 11.46 12.69 15.13 17.54 19.93 22.28 25.40 30.26 35.08 39.86 44.56 Focusing system single foucault double foucault
Table 28 foc_parm1 parameter: focus end lead frequency, defect detector, offtrack detector foc_parm1 foc_pole_lead value (binary) xxx1 1100 xxx1 1000 xxx0 0000 xxx0 1000 xxx0 1100 xxx1 1101 xxx1 1001 xxx0 0001 xxx0 1001 xxx0 1101 xxx1 1110 xxx1 1010 xxx0 0010 xxx0 1010 xxx0 1110 xxx1 1111 xxx1 1011 xxx0 0011 xxx0 1011 defect_det_sw x11x xxxx x10x xxxx x00x xxxx x01x xxxx otd_select 0xxx xxxx 1xxx xxxx Focus end lead frequency f3 kHz 1.97 2.29 2.61 2.94 3.26 3.90 4.55 5.19 5.82 6.46 7.72 8.98 10.22 11.46 12.69 15.13 17.54 19.93 22.28 Defect detector defect detector does not influence focus and radial focus hold on defect detector focus and radial hold on defect detector undefined, reserved Offtrack detector ON track active 1 ON track active 0
2003 Oct 01
58
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 30 foc_parm3 parameter: focus lead length, CA start level for focus acquisition foc_parm3 foc_lead_length value (binary) 0000 xxx1 1000 xxx1 0100 xxx1 1100 xxx1 0010 xxx1 1010 xxx1 0110 xxx1 1110 xxx1 0001 xxx1 1001 xxx1 0101 xxx1 1101 xxx1 0011 xxx1 1011 xxx1 0111 xxx1 1111 xxx1 CA_start value (binary) xxxx 000x xxxx 001x xxxx 010x xxxx 011x xxxx 100x xxxx 101x xxxx 110x xxxx 111x Focus lead length f3/f2 0 64 32 21.3 16 12.8 10.7 9.1 8 7.1 6.4 5.8 5.3 4.9 4.6 4.3 4 CAmin 0.0225 0.03 0.045 0.06 0.09 0.125 0.18 1.0 1 2 i 64 65...127 127 128...255
SAA7824
Table 32 FE_start parameter: minimum threshold for focus start FE_start value (decimal) Minimum threshold for (d1 - d2)/(d1 + d2) always 1/127 2/127 i/127 64/127 65 to 127/127 continuous ramping not allowed
Table 33 foc_int_strength parameter: focus integrator strength foc_int_strength value (decimal) 0 1 2 i 21 22...255 Focus integrator strength f5 Hz integrator hold 1.2 2.4 1.2 x i 25 undefined
Table 34 foc_gain parameter: focus gain foc_gain value (decimal) 1 2 3 i 255 0 G 2048 1024 2048/3 2048/i 2048/255 undefined
Table 31 CA_drop parameter: CA level for dropout detection CA_drop value (binary) xxx0 0000 xxx0 0100 xxx0 1000 xxx0 1100 xxx1 0000 xxx1 0100 xxx1 1000 xxx1 1100 2003 Oct 01 CAmin 0.0225 0.03 0.045 0.06 0.09 0.125 0.18 1.0 59
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 35 rad_pole_noise parameter: radial low-pass start frequency rad_pole_noise value (binary) 1101 1100 1011 1000 1010 0000 1010 1000 1000 1100 1001 1101 1001 1001 0100 0001 0100 1001 0100 1101 0101 1110 0101 1010 0100 0010 0100 1010 xxx0 1110 xxx1 1111 xxx1 1011 xxx0 0011 xxx0 1011 Radial low-pass start frequency f4 kHz 3.90 4.55 5.19 5.82 6.46 7.72 8.98 10.22 11.46 12.69 15.13 17.54 19.93 22.28 25.40 30.26 35.08 39.86 44.56
SAA7824
Table 36 rad_lead_length parameter: radial lead length rad_lead_length rad_lead_length value (binary) value (hex) 0000 xxxx 1000 xxxx 0100 xxxx 1100 xxxx 0010 xxxx 1010 xxxx 0110 xxxx 1110 xxxx 0001 xxxx 1001 xxxx 0101 xxxx 1101 xxxx 0011 xxxx 1011 xxxx 0111 xxxx 1111 xxxx 0x 8x 4x Cx 2x Ax 6x Ex 1x 9x 5x Dx 3x Bx 7x Fx Radial lead length f3/f2 128 64 42.7 32 25.6 21.3 18.3 16 14.2 12.8 11.6 10.7 9.8 9.1 8.5 8
2003 Oct 01
60
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 37 rad_parm_play, rad_parm_jump parameters: radial end lead frequency rad_parm_play rad_parm_play rad_parm_jump rad_parm_jump value (binary) value (hex) 1101 1100 1101 1000 1100 0000 1100 1000 1100 1100 1101 1101 1001 1001 1010 0001 1010 1001 1010 1101 1001 1110 0101 1010 0100 0010 0100 1010 1000 1110 0101 1111 0101 1011 0100 0011 0100 1011 DC D8 C0 C8 CC DD 99 A1 A9 AD 9E 5A 42 4A 8E 5F 5B 43 4B Radial end lead frequency f3 kHz 1.97 2.29 2.61 2.94 3.26 3.90 4.55 5.19 5.82 6.46 7.72 8.98 10.22 11.46 12.69 15.13 17.54 19.93 22.28
SAA7824
Table 39 rad_int_strength parameter: radial integrator strength rad_int_strength value (decimal) 0 1 2 i 255 Radial integrator strength f5 Hz integrator hold 0.3 0.6 0.31 x i 79.05
Table 40 Sledge_parm1 parameter: sledge integrator bandwidth, shock filter (low-pass, high-pass selection); RAM address 36H sledge_parm1 sledge_int x00x xxxx x10x xxxx x01x xxxx x11x xxxx Sledge integrator f1 Hz integrator disabled 0.15 0.31 0.45
Table 38 rad_gain parameter: radial PID gain rad_gain value (decimal) 1 2 3 i 255 0 Radial PID gain G 256 256/2 256/3 256/i 256/255 undefined
2003 Oct 01
61
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 41 sledge_parm2 parameter: sledge gain, low-pass frequencies, operation mode; RAM address 17H sledge_parm2 sledge_gain 0xxx x000 0xxx x001 0xxx x010 0xxx x011 0xxx x100 0xxx x101 0xxx x110 0xxx x111 1xxx x000 1xxx x001 1xxx x010 1xxx x011 1xxx x100 1xxx x101 1xxx x110 1xxx x111 sledge_low_pass x00x 0xxx x10x 0xxx x01x 0xxx x11x 0xxx x00x 1xxx x10x 1xxx x01x 1xxx x11x 1xxx sledge_op_mode xxx0 0xxx xxx0 1xxx xxx1 1xxx Sledge gain GS 0.218 0.281 0.436 0.562 0.875 1.125 1.750 2.250 3.500 4.500 7.000 9.000 14.00 18.00 28.00 36.00 Sledge low-pass frequency f2 Hz 5.0 10.1 15.3 20.5 0.3 0.6 0.9 1.2 Sledge operation mode PI mode operation pulsed mode operation, microcontroller controlled pulsed mode operation, automatic mode
SAA7824
Table 42 sledge_pulse1 parameter: sledge pulse high time, low time; RAM address 46H sledge_pulse1 Hex time_lo 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 xxxx 1111 xxxx time_hi xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1000 xxxx 1001 xxxx 1010 xxxx 1011 xxxx 1100 xxxx 1101 xxxx 1110 xxxx 1111 x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF 0x 1x 2x 3x 4x 5x 6x 7x 8x 9x Ax Bx Cx Dx Ex Fx 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Time high ms 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Time low ms
2003 Oct 01
62
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 43 sledge_pulse2 parameter: sledge pulse height; RAM address 64H sledge_pulse2 0111 1111 .... 0100 0000 a 0000 0000 .... 1000 0000 00 .... 80 full-scale, negative Hex 78 .... 40 half-scale, positive level = a/7F, positive zero Pulse height full-scale, positive vel_parm1 Hex vel_prop xxxx 0011 i xxxx 1111 xF x3
SAA7824
Gain constant for short jump Kv 30.0/Kv i x 10.0/Kv 150.0/Kv
Table 45 vel_parm2 parameter: time constant during sledge access/actuator access, minimum jump speed during short jump; RAM address 32H vel_parm2 vel_setp (binary) 0000 xxxx Hex Deceleration time fast actuator steered ms 7.5 8.2 9 9.7 10.5 11.2 12.5 14 15.5 16.5 20.7 25 31.2 41 63 128 Deceleration time sledge steered ms 7.5 8.2 9 9.7 10.5 11.2 12.5 14 15.5 16.5 20.7 25 31.2 41 63 128
0x 8x 4x Cx 2x Ax 6x Ex 1x 9x 5x Dx 3x Bx 7x Fx
Table 44 vel_parm1 parameter: gain constant for short jump, integrator cross-over frequency during jump; RAM address 1FH vel_parm1 Hex vel_prop 0000 xxxx 1000 xxxx 0100 xxxx 1100 xxxx 0010 xxxx 1010 xxxx 0110 xxxx 1110 xxxx 0001 xxxx 1001 xxxx 0101 xxxx 1101 xxxx 0011 xxxx 1011 xxxx 0111 xxxx 1111 xxxx vel_int 0x 8x 4x Cx 2x Ax 6x Ex 1x 9x 5x Dx 3x Bx 7x Fx Gain constant for short jump Kv 0.1875 0.4375 0.6875 0.9375 1.1875 1.4375 1.6875 1.9375 2.1875 2.4375 2.6875 2.9375 3.1875 3.4375 3.6875 3.9375 Integrator cross-over frequency during jump f0 x0 x1 x2 integrator hold 10.0/Kv 20.0/Kv 63
1000 xxxx 0100 xxxx 1100 xxxx 0010 xxxx 1010 xxxx 0110 xxxx 1110 xxxx 0001 xxxx 1001 xxxx 0101 xxxx 1101 xxxx 0011 xxxx 1011 xxxx 0111 xxxx 1111 xxxx vel_min xxxx 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 1xxx
V1 minimum jump speed kHz x0 x1 x2 x3 x4 x5 x6 x7 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 undefined
xxxx 0000 xxxx 0001 xxxx 0010 2003 Oct 01
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 46 brake_dist_max parameter: maximum sledge distance allowed in fast actuator steered mode; RAM address 21H brake_dist_max value (decimal) 0...127 -1 -2 .... -i .... -127 -128 Maximum sledge distance allowed in fast actuator steered mode, number of tracks not allowed 1 x 16 2 x 16 .... i x 16 .... 127 x 16 128 x 16
SAA7824
Table 49 jumpwatchtime parameter: radial jump watchdog readout time difference; RAM address 57H jumpwatchtime 80H to FFH 0H 1H i 7FH Radial jump watchdog readout time difference ms none 0 0.25 i x 0.25 32
Table 50 playwatchtime parameter: radial play watchdog maximum time-out; RAM address 54H playwatchtime 80H 81H 82H i 00H j 7fH Radial play watchdog maximum time-out ms 0 0.5 1 (i - 80H) x 0.5 64 (j + 80H) x 0.5 128
Table 47 sledge_Umax parameter: voltage on sledge during long jump sledge_Umax (decimal) 127 i 0 -1 -i -128 voltage on sledge 255/256 x VDD (i + 128)/256 x VDD 0.5 x VDD (128 - 1)/256 x VDD (-i + 128)/256 x VDD 0
Table 51 radcontrol parameter: automatic radial servo switch-off control; RAM address 59H Automatic radial servo switch-off control radial servo not influenced by watchdog switch-off radial servo on jump error; no action on play error switch-off radial servo on play error; no action on jump error switch-off radial servo on play or jump error
Table 48 sledge_level parameter: voltage on sledge when steered sledge_level (decimal) 127 i 0 -1 -i -128 voltage on sledge 127/256 x VDD i/256 x VDD 0 -1/256 x VDD -i/256 x VDD -128/256 x VDD
radcontrol
Hex
0000 0000
00
0100 0000
40
0010 0000
20
0110 0000
60
2003 Oct 01
64
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 52 hold_mult parameter: velocity proportional part during long jump, sledge gain in steered sledge mode; RAM address 49H hold_mult vel_prop1 (binary) 0000 xxxx 1000 xxxx 0100 xxxx 1100 xxxx 0010 xxxx 1010 xxxx 0110 xxxx 1110 xxxx 0001 xxxx 1001 xxxx 0101 xxxx 1101 xxxx 0011 xxxx 1011 xxxx 0111 xxxx 1111 xxxx vel_prop2 Hex Velocity proportional part during long jump Kp 0 0.015625 0.031250 0.046875 0.062500 0.078125 0.093750 0.109375 0.125000 0.140625 0.156250 0.171875 0.187500 0.203125 0.218750 0.234375 Sledge gain in steered mode GS x0 x1 x2 x3 x4 x5 x6 x7 2 3 4 6 8 12 16 24 -1...-128 1 2 3...62 63 -1 sledge_long_brake (decimal)
SAA7824
Table 53 speed_threshold parameter: maximum sledge speed allowed in fast actuator steered mode; RAM address 48H speed_threshold value (decimal) 0...127 -1 -2 -3...-127 -128 -64 Maximum sledge speed allowed in fast actuator steered mode, number of tracks (x 1000 tracks/sec) not allowed 1 2 3...127 128 reset value
0x 8x 4x Cx 2x Ax 6x Ex 1x 9x 5x Dx 3x Bx 7x Fx
Table 54 sledge_long_brake parameter: maximum sledge distance allowed in sledge steered mode; RAM address 58H Maximum sledge distance allowed in sledge steered mode, number of tracks test always true 1 x 128 2 x 128 3 x 128...62 x 128 63 x 128 reset value
xxxx x000 xxxx x001 xxxx x010 xxxx x011 xxxx x100 xxxx x101 xxxx x110 xxxx x111
2003 Oct 01
65
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 55 defect_parm parameter: defect detector control defect_parm xxxx xx00 xxxx xx01 xxxx xx10 xxxx xx11 defect_parm xxxx 10xx xxxx 11xx xxxx 00xx xxxx 01xx defect_parm xx00 xxxx xx01 xxxx xx10 xxxx xx11 xxxx defect_parm 00xx xxxx 01xx xxxx 10xx xxxx 11xx xxxx Fast filter bandwidth 3500 Hz 7000 Hz 14000 Hz reserved for future use Slow filter time constant 16 ms 8 ms 4 ms 2 ms Alpha value 0.00006 0.00012 0.00024 0.00048
SAA7824
Table 57 time_parameter: timer interrupt values time_parameter value (decimal)(1) 129 i 143 144 i 159 160 i 175 176 i 191 192 i 207 208 i 223 224 i 239 2402 i 55 0 i 15 16 i 31 32 i 47 48 i 63 64 i 79 80 i 95 96 i 111 111 112...127 Note 1. The time_parameter values are also used for focus_start_time, motor_start_time1, motor_start_time2, radial_init_time and brake_time. Table 58 phase_shift parameter: focus/radial AGC detection phase shift; RAM address 67H phase_shift (decimal) 0 1x a(1) 2xa ixa 128 -1 x a -2 x a -i x a 128 Note 1. The value a is the value programmed in Table 60 as the 6 LSBs of osc_inc. -60.47 -120.94 -i x 60.47 Focus/radial AGC detection phase shift (s) 0 60.47 120.94 i x 60.47 (deg) 0 180 x (a/128) 180 x (2 x a/128) 180 x (i x a/128) 180 -180 x (a/128) -180 x (2 x a/128) -180 x (i x a/128) 180 Timer interrupt values wait time (ms) 4.26 x (i - 128) 68.2 + 4.57 x (i - 144) 141.4 + 4.92 x (i - 160) 224.1 + 5.33 x (i - 176 305.4 + 5.82 x (i - 192 398.5 + 6.40 x (i - 208) 500.8 + 7.11 x (i - 224 614.6 + 8.00 x (i - 240) 742.6 + 9.11 x i 888.9 + 10.6 x (i - 16) 1059 + 12.8 x (i - 32) 1263 + 16.0 x (i - 48) 1519 + 21.2 x (i - 64) 1860 + 32.0 x (i - 80) 2372 + 64.0 x (i - 96) 3398.0 infinite
Coefficient value 0.25 0.125 0.0625 reserved for future use Defect detector maximum ON time 1.0 ms 1.5 ms 2.0 ms 2.5 ms
Table 56 interrupt_mask parameter: mask to enable interrupt in interrupt status register; RAM address 53H interrupt_mask 0000 0000 xxxx xxx1 xxxx xx1x xxxx x1xx xxxx 1xxx xxx1 xxxx xx1x xxxx x1xx xxxx Interrupt enabled no interrupt focus lost subcode ready subcode absolute seconds changed subcode discontinuity radial error autosequencer state changes autosequencer error
2003 Oct 01
66
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
Table 59 level1, level2 parameter: amplitude of signal injected into focus/radial AGC; RAM address level1 = 69H, level2 = 6AH level1, level2 (decimal) 0 1 to 126 127 128 to 255 Amplitude of injected signal 0 higher highest not allowed
SAA7824
Table 62 re_gain parameter: initial value setting re_gain -128 -127 -i -1 0 1 i 127 Value not allowed 1/256 (-i + 128)/256 127/256 128/256 129/256 (i + 128)/256 255/256
Table 60 osc_inc parameter: focus/radial AGC system control, oscillator frequency; RAM address 68H osc_inc xx00 0000 xx00 0001 xx00 0010 xx00 0011 a xx11 1111 00xx xxxx 11xx xxxx 01xx xxxx Oscillator frequency Hz 0 64.6 129.2 193.8 a x 64.6 4069.8 AGC control AGC system off focus AGC active radial AGC active
Table 63 sum_gain parameter: initial value setting sum_gain -128 -127 -i -1 0 1 i 127 Value not allowed 1/256 (-i + 128)/256 127/256 128/256 129/256 (i + 128)/256 255/256
Table 61 re_offset parameter: initial value setting re_offset 127 i 0 -i -128 Value 128/256 i/256 0 -i/256 -128/256
2003 Oct 01
67
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDDD VI(max) PARAMETER digital supply voltage maximum input voltage any input 5 V tolerant pins VO IDDD ISSD Ves Tamb Tstg Notes 1. Must not exceed 4.2 V. 2. Including voltage on outputs in 3-state mode. 3. Only valid when both supply voltages are present. 4. The peak current is limited to 25 times the corresponding maximum current. 5. Human body model. 6. Machine model. any output voltage digital supply current per supply pin digital ground current per supply pin electrostatic handling voltage ambient temperature storage temperature note 4 note 4 note 5 note 6 notes 1, 2 and 3 -0.5 -0.5 -0.5 - - -2000 -200 0 -55 VDDD + 0.5 +6.0 VDDD 20 20 +2000 +200 70 +125 CONDITIONS internal rail external rail MIN. -0.5 -0.5 MAX. +2.5 +4.6
SAA7824
UNIT V V V V V mA mA V V C C
2003 Oct 01
68
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
10 CHARACTERISTICS VDDD = 1.65 to 1.95 V; VDDA = 3.0 to 3.6 V; VSS = 0 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL Supplies VDDD IDDD digital supply voltage digital supply current n = 1 mode n = 2 mode n = 4 mode VDDA IDDA analog supply voltage analog supply current n = 1 mode n = 2 mode n = 4 mode 1.65 - - - 3.0 - - - 1.8 4.0 5.0 6.0 3.3 34 34 34 PARAMETER CONDITIONS MIN. TYP.
SAA7824
MAX.
UNIT
1.95 - - - 3.6 - - -
V mA mA mA V mA mA mA
DEM DAC output (Vpos = 3.3 V, VSS = 0 V, Vneg = 0 V and Tamb = 25 C) DIFFERENTIAL OUTPUTS: PINS DACLN, DACLP, DACRN AND DACRP S/N (THD + N)/S signal-to-noise ratio total harmonic distortion plus noise-to-signal ratio note 1 note 2 - - 90 - - -80 dB dB
Headphone buffer (Vpos = 3.3 V, VSS = 0 V, Vneg = 0 V and Tamb = 25 C) OUTPUTS: PINS BUFOUTR AND BUFOUTL S/N (THD + N)/S signal-to-noise ratio total harmonic distortion plus noise-to-signal ratio note 3 - - 85 - - -80 dB dB
INPUTS: PINS BUFINR AND BUFINL Zi input impedance - 47 - k Servo and decoder analog functions (VDDA = 3.3 V, VSSA = 0 V and Tamb = 25 C) REFERENCE GENERATOR: PIN IREF VIREF IREF RIREF(ext) Vi(D)(max) Vi(R)(max) Vref(int) BHF Gtol(HF) reference voltage level input reference current external resistance 1.16 - - voltage mode voltage mode Vref_sel = 10 Vref_sel = 11 at 0 dB 0 0 - - 5 -20 1.26 50 24 - - note 4 note 5 - - 1.36 - - 960 960 - - - +20 V A k
DIODE VOLTAGE INPUT: PINS D1 TO D4, R1 AND R2 maximum input voltage for central diode input signal maximum input voltage for satellite diode input signal internally generated reference voltage high frequency bandwidth (D1 to D4) high frequency gain tolerance mV mV V V MHz %
2003 Oct 01
69
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SYMBOL BLF (THD + N)/SLF PARAMETER low frequency bandwidth (D1 to D4, R1 and R2) low frequency total harmonic distortion plus noise-to-signal ratio low frequency signal-to-noise ratio low frequency gain tolerance low frequency variation of gain between channels low frequency channel separation VLASER = 1 V - (VDDA - 0.6 V) Io = 50 mA; B = 20 MHz Io = 120 mA maximum power; sel180 = 0 maximum power; sel180 = 1 CONDITIONS at 0 dB at 0 dB 20 - MIN. - -50 TYP. - -40
SAA7824
MAX.
UNIT kHz dB
S/NLF Gtol(LF) Gv(LF) cs(LF)
55 -20 -3 -
- - - 60
- +20 +3 -
dB % % dB
Laser drive circuit (VDDA = 3.3 V; VSSA = 0 V; Tamb = 25 C; RIREF = 30 k) Io(LASER) SNR ILFPOWER(max) VMONITOR1 VMONITOR2 Ri Vsense Pstep Ipd ILASER(off) Digital inputs PIN RESET (5 V TOLERANT; TTL INPUTS WITH PULL-UP RESISTOR AND HYSTERESIS) VIH VIL Vhys IPU tW(L) VIH VIL HIGH-level input voltage LOW-level input voltage hysteresis voltage pull-up current pulse width (active LOW) Vi = 0 to VDDD; notes 6 and 7 RESET only 2.0 - 0.3 -31 1 - - - - - - - - 0.8 - -68 - - 0.8 V V V A s V V output current signal-to-noise ratio maximum laser supply current monitor diode voltage 1 monitor diode voltage 2 input resistance sense voltage laser output power range power-down supply current laser off current 10 - - 140 170 10 -100 43 - - 50 40 - 150 180 - - - - - 120 - 140 160 190 - +100 100 10 30 mA dB mA mV mV M mV % A
mA
PINS V1 AND V2 (CMOS INPUTS) HIGH-level input voltage LOW-level input voltage 2.0 -
2003 Oct 01
70
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SYMBOL PARAMETER CONDITIONS MIN. - - 50 TYP. - 0.8 75
SAA7824
MAX.
UNIT
PINS TEST1 TO TEST4 (5 V TOLERANT; TTL INPUTS WITH PULL-DOWN RESISTORS) VIH VIL IPD HIGH-level input voltage LOW-level input voltage pull-down current Vi = 0 to VDDD; notes 6 and 7 (Vi = 5 V; note 8) 2.0 - 20 V V A
PINS RCK, WCLI, SDI AND SCLI (5 V TOLERANT; TTL INPUTS) VIH VIL IIL IIH
PINS
HIGH-level input voltage LOW-level input voltage LOW-level input current HIGH-level input current Vi = 0; no pull-up Vi = VDDD; no pull-down
2.0 - - - 2.0 - Vi = 0; no pull-up Vi = VDDE; no pull-down - - 0.3
- - - - - - - - -
- 0.8 1 1 - 0.8 1 1 -
V V A A V V A A V
SCL, SILD, RAB AND CDTCLK (5 V TOLERANT TTL INPUTS WITH HYSTERESIS) HIGH-level input voltage LOW-level input voltage LOW-level input current HIGH-level input current hysteresis voltage
VIH VIL IIL IIH Vhys 3-state outputs
SCLK, WCLK, DATA, CLK16, RA, FO, SL, SBSY, SFSY, CLK4/12, STATUS, MOTO1 AND MOTO2 (5 V TOLERANT CMOS OUTPUTS; 10 ns SLEW RATE LIMITED)
PINS
VOL VOH IOL IOH ttran(L-H) IOZ
PINS
LOW-level output voltage HIGH-level output voltage LOW-level output current HIGH-level output current LOW-to-HIGH transition time 3-state leakage current
IOL = 4 mA IOH = -4 mA VOL = 0.4 V; note 9 VOL = VDDD - 0.4 V; note 9 CL = 30 pF Vi = 0; no pull-up or pull-down
- VDDD - 0.4 4 -4 10.2 -
- - - - - -
0.4 - - - 14.5 1
V V mA mA ns A
DOBM, V4 AND V5 (5 V TOLERANT CMOS OUTPUTS; 5 ns SLEW RATE LIMITED) LOW-level output voltage HIGH-level output voltage LOW-level output current HIGH-level output current LOW-to-HIGH transition time 3-state leakage current IOL = 4 mA IOH = -4 mA VOL = 0.4 V; note 9 VOL = VDDD - 0.4 V; note 9 CL = 30 pF Vi = 0; no pull-up or pull-down - VDDD - 0.4 4 -4 - - - - - - 10 - 0.4 - - - 13.8 1 V V mA mA ns A
VOL VOH IOL IOH ttran(L-H) IOZ
2003 Oct 01
71
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA7824
MAX.
UNIT
Digital inputs and outputs
PIN
V3 (5 V TOLERANT; TTL INPUT; 3-STATE OUTPUT) HIGH-level input voltage LOW-level input voltage LOW-level input current HIGH-level input current LOW-level output voltage HIGH-level output voltage LOW-level output current HIGH-level output current LOW-to-HIGH transition time 3-state leakage current Vi = 0; no pull-up Vi = VDDD; no pull-down IOL = 4 mA IOH = -4 mA VOL = 0.4 V; note 9 VOL = VDDD - 0.4 V; note 9 CL = 30 pF Vi = 0 2.0 - - - - VDDD - 0.4 4 -4 2.6 - - - - - - - - - - - - 0.8 1 1 0.4 - - - 6.3 1 V V A A V V mA mA ns A
VIH VIL IIL IIH VOL VOH IOL IOH ttran(L-H) IOZ
PINS LIMITED)
LKILL, RKILL AND CFLAG (5 V TOLERANT; TTL INPUT WITH PULL-UP; 3-STATE OPEN-DRAIN OUTPUT; 10 ns SLEW RATE HIGH-level input voltage LOW-level input voltage pull-up current LOW-level output voltage HIGH-level output voltage LOW-level output current HIGH-level output current LOW-to-HIGH transition time 3-state leakage current Vi = 0 to VDDD; notes 6 and 7 IOL = 4 mA IOH = -4 mA VOL = 0.4 V; note 9 VOL = VDDD - 0.4 V; note 9 CL = 30 pF Vi = 0 2.0 - -13 - VDDD - 0.4 4 -4 8.6 - 2.0 - Vi = 0 Vi = VDDD IOL = 4 mA IOH = -4 mA VOL = 0.4 V; note 9 VOL = VDDD - 0.4 V; note 9 CL = 30 pF Vi = 0 - - - VDDD - 0.4 4 -4 8.6 - - - - - - - - 10 - - - - - - - - - 10 - - 0.8 -36 0.4 - - - 13.8 1 - 0.8 1 1 0.4 - - - 13.8 1 V V A V V mA mA ns A V V A A V V mA mA ns A
VIH VIL IPU VOL VOH IOL IOH ttran(L-H) IOZ
PINS
CDTRDY, CDTDATA, EF AND SUB (5 V TOLERANT; TTL INPUT; 3-STATE OUTPUT; 10 ns SLEW RATE LIMITED) HIGH-level input voltage LOW-level input voltage LOW-level input current HIGH-level input current LOW-level output voltage HIGH-level output voltage LOW-level output current HIGH-level output current LOW-to-HIGH transition time 3-state leakage current
VIH VIL IIL IIH VOL VOH IOL IOH ttran(L-H) IOZ
2003 Oct 01
72
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SYMBOL
PIN
SAA7824
PARAMETER
CONDITIONS
MIN. - - - - - 2
TYP. -
MAX.
UNIT
SDA (5 V TOLERANT; 400 kHZ I2C-BUS PAD) HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage output fall time from VIH to VIL steady-state current input signal IOL = 3 mA bus capacitance, Cb, from 10 pF to 400 pF) Vi = VDDD; note 11 Vi = 5 V; note 11 VTOL = 5 V; note 10 0.7VTOL - 0.05VTOL - 20 + 0.1Cb - - V V V V ns A A 0.3VTOL - 0.4 250 4 22
VIH VIL Vhys VOL tf Iikg
10
Crystal oscillator INPUT: PIN OSCIN (EXTERNAL CLOCK) VIH VIL VOL VOH fxtal gm Notes 1. Assumes use of external components as shown in the application diagram; see Fig.38. 2. RL = 10 k. 3. RL = 1 k. 1.65 x 3.3 4. The typical value is as follows: ------------------------V DDA 2.5 x 3.3 5. The typical value is as follows: ---------------------V DDA 6. Pull-up/down devices are protected by a pass-gate and do not behave as a normal resistor for external applications 7. Pull-up/down resistors are connected to external power supply (VDDE/GND). 8. Minimum condition for Vi = 4.5 V, maximum condition for Vi = 5.5 V. 9. Accounts for 100 mV voltage drop in both supply lines. 10. Minimum condition for VTOL = 4.5 V, maximum condition for VTOL = 5.5 V. 11. Leakage path from pad to ground. HIGH-level input voltage LOW-level input voltage - 0.8VDDD - 0.85VDDD 100 ppm - 19.1 - - - - 8.4672 - 0.2VDDD - 0.4 - - 23.0 V V
OUTPUT: PIN OSCOUT; see Fig.4 LOW-level output voltage HIGH-level output voltage crystal frequency mutual conductance at start-up V V MHz mA/V
2003 Oct 01
73
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
11 OPERATING CHARACTERISTICS (SUBCODE INTERFACE TIMING) VDDD = 1.65 to 1.95 V; VSS = 0 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA7824
MAX.
UNIT
Subcode interface timing (single speed x n); see Fig.34; note 1 INPUT: PIN RCK tCLKH tCLKL tr tf td(SFSY-RCK) Tcy(block) tW(SBSY) Tcy(frame) tW(SFSY) tSFSYH tSFSYL td(SFSY-SUB) td(RCK-SUB) th(RCK-SUB) Note 1. In the normal operating mode the subcode timing is directly related to the overspeed factor `n'. In the lock-to-disc mode `n' is replaced by the disc speed factor `d', input clock HIGH time input clock LOW time input clock rise time input clock fall time delay time SFSY to RCK 2/n 2/n - - 10/n 4/n 4/n - - - 13.3/n - 136/n - - - - - - 6/n 6/n 80/n 80/n 20/n s s ns ns s ms s s s s s s s s
OUTPUTS: PINS SBSY, SFSY AND SUB (CL = 20 pF) block cycle time SBSY pulse width frame cycle time SFSY pulse width SFSY HIGH time SFSY LOW time delay time SFSY to SUB (P data) valid delay time RCK falling to SUB hold time RCK to SUB 3-wire mode 12.0/n - 122/n - - - - - - 14.7/n 300/n 150/n 366/n 66/n 84/n 1/n 0 0.7/n
2003 Oct 01
74
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SAA7824
handbook, full pagewidth
tW(SBSY)
Tcy(block)
SBSY tSFSYH SFSY (4-wire mode) tW(SFSY) SFSY (3-wire mode) tSFSYL Tcy(frame)
SFSY 0.8 V td(SFSY-RCK) tr tf VDD - 0.8 V RCK 0.8 V td(SFSY-SUB) th(RCK-SUB) td(RCK-SUB) VDD - 0.8 V SUB 0.8 V
MGL718
Fig.34 Subcode interface timing diagram.
2003 Oct 01
75
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
12 OPERATING CHARACTERISTICS (I2S-BUS TIMING) VDDD = 1.65 to 1.95 V; VSS = 0 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA7824
MAX.
UNIT
I2S-bus timing (single speed x n); see Fig.35; note 1 CLOCK OUTPUT: PIN SCLK (CL = 20 pF) Tcy output clock period sample rate = fs sample rate = 2fs sample rate = 4fs tCH clock HIGH time sample rate = fs sample rate = 2fs sample rate = 4fs tCL clock LOW time sample rate = fs sample rate = 2fs sample rate = 4fs OUTPUTS: PINS WCLK, DATA AND EF (CL = 20 pF) tsu set-up time sample rate = fs sample rate = 2fs sample rate = 4fs th hold time sample rate = fs sample rate = 2fs sample rate = 4fs Note 1. In the normal operating mode the I2S-bus timing is directly related to the overspeed factor `n'. In the lock-to-disc mode `n' is replaced by the disc speed factor `d'. 95/n 48/n 24/n 95/n 48/n 24/n - - - - - - - - - - - - ns ns ns ns ns ns - - - 166/n 83/n 42/n 166/n 83/n 42/n 472.4/n 236.2/n 118.1/n - - - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns
clock period Tcy t CL t CH V DD - 0.8 V SCLK 0.8 V th WCLK DATA EF t su V - 0.8 V
DD
0.8 V
MBG407
Fig.35 I2S-bus timing diagram.
2003 Oct 01
76
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
13 OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING) VDD = 1.65 to 1.95 V; VSS = 0 V; Tamb = 0 to 70 C; unless otherwise specified. NORMAL MODE SYMBOL PARAMETER CONDITIONS MIN. MAX. MIN.
SAA7824
LOCK-TO-DISC MODE UNIT MAX.
Microcontroller interface timing (4-wire bus mode; writing to decoder registers 0 to F; reading Q-channel subcode and decoder status); see Figs.36 and 37; note 1 INPUTS SCL AND RAB tCL tCH tr tf tdRD tPD tdRZ input clock LOW time input clock HIGH time input rise time input fall time 480/n + 20 480/n + 20 - - - 720/n - 20 - - - 480/n 480/n 2400/n + 20 2400/n + 20 - - - - - 480/n 480/n ns ns ns ns
READ MODE (CL = 20 pF) delay time RAB to SDA valid propagation delay SCL to SDA delay time RAB to SDA high-impedance 50 50 4800/n + 20 50 ns ns
960/n + 20 720/n + 20 50 -
WRITE MODE (CL = 20 pF) tsuD thD tsuCR tdWZ set-up time SDA to SCL hold time SCL to SDA set-up time SCL to RAB delay time SDA to RAB high-impedance note 2 20 - 720/n - 240/n + 20 0 - 20 - 720/n - 4800/n + 20 - - ns ns ns ns
960/n + 20 - - - 1200/n + 20 0
Microcontroller interface timing (4-wire bus mode; servo commands); see Figs.36 and 38; note 2 INPUTS SCL AND SILD tL tH tr tf tdLD tPD tdLZ tsuCLR input LOW time input HIGH time input rise time input fall time 710 710 - - - - - 480 - - 240 240 710 710 - - - - - 480 - - 240 240 ns ns ns ns
READ MODE (CL = 20 pF) delay time SILD to SDA valid propagation delay SCL to SDA delay time SILD to SDA high-impedance set-up time SCL to SILD 25 950 50 - 25 950 50 - ns ns ns ns
2003 Oct 01
77
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
NORMAL MODE SYMBOL thCLR PARAMETER hold time SILD to SCL CONDITIONS MIN. 830 - MAX. 830 MIN. -
SAA7824
LOCK-TO-DISC MODE UNIT MAX. ns
WRITE MODE (CL = 20 pF) tsD thD tsCL thCL tdPLP tdWZ Notes 1. The 4-wire bus mode microcontroller interface timing for writing to decoder registers 0 to F, and reading Q-channel subcode and decoder status, is a function of the overspeed factor `n'. In the lock-to-disc mode the maximum data rate is lower. 2. Negative set-up time means that the data may change after clock transition. set-up time SDA to SCL hold time SCL to SDA set-up time SCL to SILD hold time SILD to SCL delay between two SILD pulses delay time SDA to SILD high-impedance 0 950 480 120 70 0 - - - - - - 0 950 480 120 70 0 - - - - - - ns ns ns ns ns ns
tr
tf V - 0.8 V
DD
RAB tr tf t CH V DD - 0.8 V 0.8 V t CL t SDA (SAA782X) high-impedance PD V DD - 0.8 V 0.8 V
MBL451
0.8 V
SCL
t dRD
t dRZ
Fig.36 4-wire microcontroller timing; read mode (Q-channel subcode and decoder status information).
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Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SAA7824
handbook, full pagewidth
tr t suCR RAB
t CH
tf V DD - 0.8 V 0.8 V
tf
t CH
tr VDD - 0.8 V
t CL
SCL 0.8 V t CL t suD SDA (microcontroller) t hD t dWZ
V DD - 0.8 V 0.8 V high-impedance
MBG405
Fig.37 4-wire bus microcontroller timing; write mode (decoder registers 0 to F).
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Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SAA7824
handbook, full pagewidth
VDD - 0.8 V SILD 0.8 V thCLR tsuCLR VDD - 0.8 V SCL 0.8 V tdLD VDD - 0.8 V SDA (SAA782X) 0.8 V
MBL452
tPD
tdLZ
Fig.38 4-wire bus microcontroller timing; read mode (servo commands).
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Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SAA7824
handbook, full pagewidth
VDD - 0.8 V 0.8 V tsCL tH tL tdPLP VDD - 0.8 V
SILD
SCL 0.8 V thCL tsD thD VDD - 0.8 V SDA (microcontroller) 0.8 V tL tdWZ
MBG416
Fig.39 4-wire bus microcontroller timing; write mode (servo commands).
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Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
14 APPLICATION INFORMATION
C30 220 F (50 V) VCC X1 1 X1 2 X1 3 X1 4 RAD- FOC+ FOCRAD+ RADO- FOCO+ GND FOCORADO+ VCC VCC X2 5 X2 6 X2 3 X2 4 B SLEDGE+ WH SLEDGE- G MOTOR+ Y MOTOR- SLO+ SLO- GND MOTO- MOTO+ VCC 3.3 Vout 3.3 VFB 1.8 Vout 1.8 VFB MUTE RA1 FO1 SL1 VBout GND 1.65 Vout mute MOTO1 MOTO2 C32 0.47 F (50 V) C33 470 pF (50 V) C28 470 pF (50 V) C27 470 pF (50 V) C26 470 pF (50 V)
SAA7824
handbook, full pagewidth
A 28 27 26 25 24 23 22 EARTH 30 21 20 19 18 17 16 15 J B C D E F G H
1 2 3 4 5 6 7 29 8 9 10 11 12 13 14
TZA1048
K L C25 470 pF (50 V)
X2 2 X2 1
HOME_SW BL VSSD
to CD mechanism (VAM220X)
M X3 1 X3 2 TEST4 TEST3 TEST2 V5 V4 V3 VSSD TEST1 3.3 VDD LASER TRAY_SW N O
80
79
78
77
76
75
74 27
X1 10
LD
C6 10 F (15 V)
C7 10 nF (50 V)
LFPOWER EXFILTER MONITOR SENSE VSSA1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 DACVpos DACGND BUFVpos DACRP DACRN DACVref DACLN DACLP 28 P 3.3 VDD C18 88 F C17 (16 V) 3.3 nF (100 V) VSSD R S
X1 9 X1 15 X1 5
MON
VSSD 3.0 VDD X1 12 X1 6 X1 14 X1 8 X1 11 X1 13 X1 7 R1 R2 C24 100 nF (50 V) D1 D2
3.3 VDD
VSSD
C8 10 F (50 V)
R8
IREF VREFO D1 D2 D3 D4 R1 R2 CSLICE
24 k (0.5 W) VDDA1
SAA7824HL
3.0 VDD 8.4672 MHz
VDDA2 VSSA2 OSCOUT OSCIN
VSSD
C23 1 nF (50 V)
C22 10 F (50 V)
C21 33 pF (100 V)
C20 33 pF (100 V) VSSD
VSSA3
33 F (16 V) 22 F (35 V) audio in R audio in L R9 47 k (0.6 W) TR4 BC337 VSSD VSSD R15 100 k (0.4 W) R7 47 k (0.6 W) R6 47 k (0.4 W) TR3 BC337 VSSD VSSD R10 100 k (0.4 W) C18 C19 22 F (38 V) C15 3.3 nF (100 V) VSSD
C17
R8 47 k (0.4 W)
MBL453
Fig.40 Typical application diagram incorporating a voltage mechanism (continued in Fig.41).
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Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
SAA7824
handbook, full pagewidthA
5V B C D E F G H J 3.3 VDD C2 33 F (16 V) VSSD K L 3.3 VDD R11 10 (0.6 W) R13 10 k (0.6 W) R14 10 k (0.6 W) C5 100 nF (50 V) V SSD R16 24 k (0.6 W) R4 24 k (0.6 W) R3 24 k (0.6 W) R2 24 k (0.6 W) R1 24 k (0.6 W) 1.8 VDD C8 33 F (16 V) VSSD 1.8 VDD TR1 BC337 C1 100 nF (50 V) VSSD
X4 1 X4 2 X4 3 X4 4 X4 5 X4 6 audio_L
VCC IN (12 V) VCC IN (5 V)
VSSD audio_R VSSD
audio out (R)
audio out (L)
TR2 BC337
M N
MOTO2
MOTO1
VDDD3
VDDD2
O V2 V1
VSSD3
VSSD2
DOBM
C4 100 nF (50 V) VSSD 60 59 58 57 56 55 54 53 52 SBSY SFSY SUB RCK 3.3 VDD
FO 65
72
71
70
69
68
67
66
64
RA
SL
63
62
61
to mini micro
MUTE STATUS TRAY 5 W VSSD X5 1 X5 2 X5 3 X5 4 SCL SDA RESET X5 5 X5 6 X5 7 X5 8 CDTCLK CDTDATA CDTRDY X5 9 X5 10 X5 11 X5 12 3.3 VDD R12 10 (0.6 W) 5V DATA VSSD VSSD VSSD
STATUS SILD RAB SCL SDA RESET CLK4/12 CLK16 SCLK WCLK DATA EF SCLI WCLI SDI VDDD1 C9 100 nF (50 V)
SAA7824HL
51 50 49 48 47 46 45 44 43 42 41
for playability test
WCLK SCLK CFLAG X6 1 X6 2 X6 3 X6 4 X6 5 X6 6
29
30
31
32
33
34
35
36
37
38
39 CFLAG
BUFINR
BUFINL
LKILL
RKILL
BUFOUTR
BUFOUTL
BUFGND
CDTRDY
CDTDATA
P VSSD
CDTCLK
VSSD1
40
to headphone
33 F 10 (16 V) (0.6 W) C11 C10 R23 R22 C36 10 nF (50 V) VSSD C37 10 nF (50 V) VSSD VSSD O BMD D F B B B POLB stereo 3.5 s
R S audio R C16 10 F (50 V) audio L C14 4 10 F (50 V)
2 3
R10 10 k 5 VSSD
1
10 33 F (16 V) (0.6 W)
MBL454
Fig.41 Typical application diagram incorporating a voltage mechanism (continued from Fig.40).
2003 Oct 01
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Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
15 PACKAGE OUTLINE LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm
SAA7824
SOT315-1
c
y X A 60 61 41 40 Z E
e E HE wM bp pin 1 index 80 1 20 ZD bp D HD wM B vM B vM A 21 detail X Lp L A A2 A1 (A 3)
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.16 0.04 A2 1.5 1.3 A3 0.25 bp 0.27 0.13 c 0.18 0.12 D (1) 12.1 11.9 E (1) 12.1 11.9 e 0.5 HD HE L 1 Lp 0.75 0.30 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7 0o
o
14.15 14.15 13.85 13.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT315-1 REFERENCES IEC 136E15 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
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84
Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
16 SOLDERING 16.1 Introduction to soldering surface mount packages
SAA7824
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 16.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 16.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
16.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3)
SAA7824
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
17 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
SAA7824
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Philips Semiconductors
Product specification
CD audio decoder, digital servo and filterless DAC with integrated pre-amp and laser control
20 PURCHASE OF PHILIPS I2C COMPONENTS
SAA7824
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R04/03/pp89
Date of release: 2003
Oct 01
Document order number:
9397 750 12009

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